摘要:
VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count_0to8 is port( clk : in std_logic; clr : in std_logic; q 阅读全文
摘要:
Java方法 方法重载 package com.xiang.method; public class Demo02 { public static void main(String[] args) { int max = max(20, 100, 10); System.out.println(ma 阅读全文
摘要:
VHDL 全加器的四种实现方式 library ieee; use ieee.std_logic_1164.all; entity full_adder4th is generic(tpd : time := 10 ns); port( x, y, c_in : in std_logic; sum, 阅读全文
摘要:
VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count3 is port (clk:in bit; count:out bit_vector (2 downto 0)) 阅读全文