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【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch12

摘要： Chapter 12. User-Defined Primitives 12.7 Exercises 1. Design a 2-to-1 multiplexer by using UDP. The select signal is s, inputs are i0,i1, and the output is out. If the select signal s=x, the output ou... 阅读全文

posted @ 2011-03-28 16:53 yf.x 阅读(2388) 评论(0) 推荐(0)

【笔记】Excel技巧—003 实用的Excel选项设置

摘要：工具 / 选项。启动时不加载任务窗格：选项 / 视图 / 启动任务窗格最近使用的文件列表选项 / 常规 / 最近使用的文件列表新工作簿选项 / 常规 / 新工作簿内的工作表数默认文件位置选项 / 常规 / 默认文件位置用户名选项 / 常规 / 用户名阅读全文

posted @ 2011-03-28 09:43 yf.x 阅读(434) 评论(0) 推荐(0)

【笔记】Excel技巧—002 Excel启动时打开指定工作簿

摘要：工具 / 选项 / 常规 / 启动时打开此目录中的所有文件。将要打开的Excel文件放到XLSTART中。阅读全文

posted @ 2011-03-27 15:56 yf.x 阅读(415) 评论(0) 推荐(0)

【笔记】Excel技巧—001 设置Excel启动

摘要：在快捷方式属性 / 快捷方式 / 目标后加参数 /e 可加快启动速度。加 /s 可以安全模式运行，暂时解决程序故障。阅读全文

posted @ 2011-03-27 15:51 yf.x 阅读(680) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch10

摘要： Chapter 10. Timing and Delays10.6 Exercises1. What type of delay model is used in the following circuit? Write the Verilog description for the module Y. my answer: Distributed Delay. 2. Use the largest delay in the module to convert the circuit to a lumped delay model. Using a lumped delay model, wr 阅读全文

posted @ 2011-03-25 20:13 yf.x 阅读(3323) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch09

摘要： Chapter 9. Useful Modeling Techniques9.7 Exercises1. Using assign and deassign statements, design a positive edge-triggered D-flipflop with asynchronous clear(q=0) and preset (q=1). my answer: 2. Using primitive gates, design a 1-bit full adder FA. Instantiate the full adder inside a stimulus module 阅读全文

posted @ 2011-03-24 17:33 yf.x 阅读(6337) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch08

摘要： Chapter 8. Tasks and Functions8.5 Exercises1. Define a function to calculate the factorial of a 4-bit number. The output is a 32-bit value. Invoke the function by using stimulus and check results. my answer: # Factorial of 4 is 3628800 2. Define a function to multiply two 4-bit numbers a and b. The 阅读全文

posted @ 2011-03-22 10:03 yf.x 阅读(9277) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-III

摘要： 12. Using a case statement, design an 8-function ALU that takes 4-bit inputs a and b and a 3-bit input signal select, and gives a 5-bit output out. The ALU implements the following functions based on a 3-bit input signal select. Ignore any overflow or underflow bits. Select SignalFunction3’b000Out=a 阅读全文

posted @ 2011-03-18 16:08 yf.x 阅读(11261) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-II

摘要： 7. Design a negative edge-triggered D-flipflop(D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg). Design a clock with a period of 10 units and test the D_FF.my 阅读全文

posted @ 2011-03-17 17:00 yf.x 阅读(8853) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-I

摘要： Chapter 7. Behavioral Modeling7.11 Exercises1. Declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement ( Hint: Use the forever loop).my answer:2. Design a clock with time period = 40 and a duty cycle of 25% by using the always and i 阅读全文

posted @ 2011-03-17 11:49 yf.x 阅读(9996) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch06

摘要： Chapter 6. Dataflow Modeling6.7 Exercises1. A full subtractor has three 1-bit inputs x,y,and z(previous borrow) and two 1-bit outputs D(difference) and B(borrow). The logic equations for D and B are as follows: D=x’.y’.z + x’.y.z’ + x.y’.z’ + x.y.z B=x’.y + x’.z + y.z Write the full Verilog descript 阅读全文

posted @ 2011-03-15 20:07 yf.x 阅读(13422) 评论(1) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05

摘要： Chapter 5. Gate-level Modeling5.4 Exercises1. Create your own 2-input Verilog gates called my_or, my_and and my_not from 2-input nand gates. Check the functionality of these gates with a stimulus module. my answer: 2. A 2-input xor gate can be built from my_and, my_or and my_not gates. Construct an 阅读全文

posted @ 2011-03-13 18:45 yf.x 阅读(20793) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch04

摘要： Chapter 4. Modules and Ports4.5 Exercises1. What are the basic components of a module? Which components are mandatory? my answer: 1) Module Name, Port List, Port Declarations, Parameters, Declarations of wires, regs and other variables, Data flow statements, Instantiation of lower level modules, alw 阅读全文

posted @ 2011-03-12 13:21 yf.x 阅读(8090) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch03

摘要： Chapter 3. Basic Concepts3.5 Exercises1. Practice writing the following numbers: a) Decimal number 123 as a sized 8-bit number in binary. Use _ for readability. b) A 16-bit hexadecimal unknown number with all x’s. c) A 4-bit negative 2 in decimal. Write the 2’s complement form for this number. d) An 阅读全文

posted @ 2011-03-10 18:05 yf.x 阅读(8735) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch02

摘要： Chapter 2. Hierarchical Modeling Concepts2.8 Exercises1. An interconnect switch (IS) contains the following components, a shared memory (MEM), a system controller (SC) and a data crossbar (Xbar). a) Define the modules MEM, SC, and Xbar, using the module/endmodule keywords. You do not need to define 阅读全文

posted @ 2011-03-10 13:12 yf.x 阅读(3845) 评论(0) 推荐(1)

【翻译】ModelSim指南 VI （ModelSim）（Verilog）（Digital Logic）

摘要： 8自动仿真简介前面的课程主要讲使用ModelSim的交互模式：通过图形界面或主窗口的命令行一条条的执行单一的命令。当需要完成重复的任务时，可用DO文件提高效率。 DO文件是一次执行多条命令的脚本。这个脚本可以像带有相关参数的一系列ModelSim命令一样简单，或者是带有变量，执行条件等等的Tcl程序。可在GUI里或系统命令提示符后执行Do文件。注意：本课假设你已经添加<install_dir>/modeltech/<platform>到你的环境变量的PATH。否则，要指定工具（如，vlib，vmap, vlog，vcom，和vsim）的绝对路径。扩展阅读用户手册：阅读全文

posted @ 2011-03-09 16:20 yf.x 阅读(2523) 评论(0) 推荐(0)

【翻译】ModelSim指南 V （ModelSim）（Verilog）（Digital Logic）

摘要： 7查看和初始化内存简介本课将学习如何查看和初始化内存。把以下作为内存定义并列出： l 寄存器、线变量和标准逻辑数列 l 整数数列 l VHDL里除了标准逻辑之外的列举类型的信号元数列本课所用的设计文件安装时自带的范例。扩展阅读用户手册：Memory and Memory Data Windows。命令参考：mem display，mem load, mem save, and radix。编译并加载设计1. 创建一个新目录并拷贝所用的文件。从如下路径拷贝所有的文件。 <install_dir>/examples/tutorials/verilog/memory to th 阅读全文

posted @ 2011-03-08 17:54 yf.x 阅读(2299) 评论(0) 推荐(0)

【翻译】ＭｏｄｅｌＳｉｍ指南　ＩＶ　（ＭｏｄｅｌＳｉｍ）（Ｖｅｒｉｌｏｇ）（Ｄｉｇｉｔａｌ　Ｌｏｇｉｃ）

摘要： 6分析波形简介Wave窗口可查看仿真结果。它分为几个区域（图6-1）。各个区的大小、位置可重置。扩展阅读用户手册：Wave Window和Recording Simulation Results With Datasets 加载设计本课用的范例，类似前面基本仿真的设计。 1. 如果刚完成前面的课程，ModelSim就已经打开了，否则，启动Modelsim。 2. 加载设计。 a) 选择File > Change Directory并打开在基本仿真那课里创建的目录。 work应该已经存在了。 b) 单击work库前的‘+’并双击test_counter。 ModelSim加载设计并打开S 阅读全文

posted @ 2011-03-07 16:50 yf.x 阅读(2314) 评论(0) 推荐(2)

【翻译】ModelSim指南 III （ModelSIM）（Verilog）（Digital Logic）

摘要： 5多库协作简介本课将练习使用多个库。通过使用第三方的库，使设计包含多个库。本课先创建一个包含counter设计单元的资源库。然后，创建一个项目并编译测试台，链接包含counter的库，最后运行仿真。本课用到的设计文件范例是一个8位二进制递增计数器和相关的测试台。路径如下： Verilog – <install_dir>/examples/tutorials/verilog/libraries/counter.v and tcounter.v 扩展阅读用户手册章节—Design Libraries。创建资源库在创建资源库前，确认安装目录里的modelsim.ini文件的属性是“ 阅读全文

posted @ 2011-03-07 12:49 yf.x 阅读(1028) 评论(0) 推荐(2)

【翻译】ModelSim指南II（ModelSim）（Verilog）（digital Logical）

摘要： 4项目简介本课将练习创建一个项目。项目最少包括一个工作库和存储在.mpf文件里德状态集合。一个项目可能由以下几部分组成： l HDL源文件或源文件索引 l 其他文件如说明或其他项目文档 l 本地库 l 全局库索引本课用到的设计文件本课范例是一个简单的8位二进制递增计数器和相应的测试台。其在如下位置： Verilog – <install_dir>/examples/tutorials/verilog/projects/counter.v and tcounter.v 扩展阅读用户手册章节：Projects。创建一个新项目1. 创建一个新目录并复制本课所用的设计文件。 2. 如阅读全文

posted @ 2011-03-03 16:56 yf.x 阅读(1147) 评论(0) 推荐(1)