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【笔记】Excel技巧—008 快速填充所有空白单元格

摘要： step 1. 选择数据区域B2：M27，编辑 / 定位或用F5； step 2. 定位条件 / 空值 / 确定； step 3. 输入0 / <Ctrl+Enter>；阅读全文

posted @ 2011-04-02 08:04 yf.x 阅读(319) 评论(0) 推荐(0)

【笔记】Excel技巧—007 轻松选取“特殊”区域

摘要：编辑 / 定位（或F5）/ 输入引用位置。选择“定位条件”。阅读全文

posted @ 2011-04-01 08:26 yf.x 阅读(246) 评论(0) 推荐(0)

【笔记】DE2 硬件和处理器范例-2 External SRAM interface （DE2）（digital logic）（verilog hdl）

摘要： Introduction 本项目练习使用外部的61LV25616 SRAM，实现以下目标：用KEY0作为时钟输入，驱动一个4位的计数器，以产生一个地址码，然后在前面补充14个0扩展成18位的地址码。这个地址码作为存储器的地址在HEX4和绿色的LED上显示。使用SWITCH[15:0]作为写入SRAM的数据。使用KEY1作为写使能。注意写使能低电平有效，即按钮按下时。在红色LED和HEX3-... 阅读全文

posted @ 2011-03-31 14:43 yf.x 阅读(1529) 评论(0) 推荐(0)

【笔记】Excel技巧—006 选取单元格区域

摘要： 1. 使用<Shift>键选择大区域例如：选择A1：H50. 方法1：定位到A1 / 按住<Shift> / 按右箭头直到A1:H1 / 按下箭头到50行。也可配合<Pg Dn>使用。方法2：定位到H1 / 按住<Shift> / 按<Home> / 同方法1的操作。 2. 选择当前数据区域选中数据区域中的任一单元格 / 按 <Ctrl + *> 3. 选定非连续区域按住<Ctrl>同时用... 阅读全文

posted @ 2011-03-31 09:28 yf.x 阅读(458) 评论(0) 推荐(0)

【笔记】error 引脚冲突 ~LVDS150p/nCEO~ （digital logic) (DE2)

摘要：如下：Error: Can't place multiple pins assigned to pin location Pin_W20 (IOC_X65_Y2_N2)Info: Pin EA[7] is assigned to pin location Pin_W20 (IOC_X65_Y2_N2)Info: Pin ~LVDS150p/nCEO~ is assigned to pin loca... 阅读全文

posted @ 2011-03-30 16:54 yf.x 阅读(755) 评论(0) 推荐(0)

【笔记】Excel技巧—005 使用工作区文件

摘要：当使用多个Excel文件来完成某项工作，不希望每次都重排窗口。打开全部所需的Excel文件并排列好窗口。文件 / 保存工作区 / 文件名 /保存。（工作簿文件的位置改变后，这个工作区文件失效）。阅读全文

posted @ 2011-03-30 08:35 yf.x 阅读(380) 评论(0) 推荐(0)

【笔记】Excel技巧—004 多用途的文档属性

摘要：设置属性，便于管理文档。属性 / 自定义可设置更多的项目，利于“高级文件搜索”打开“高级文件搜索”：文件 / 文件搜索，如果显示的是“基本文件搜索”，在“请参阅”下方，单击“高级文件搜索”。预防忘记为新工作簿添加属性：工具 / 选项 / 常规 / 提示输入工作簿摘要i信息。阅读全文

posted @ 2011-03-29 09:17 yf.x 阅读(322) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch12

摘要： Chapter 12. User-Defined Primitives 12.7 Exercises 1. Design a 2-to-1 multiplexer by using UDP. The select signal is s, inputs are i0,i1, and the output is out. If the select signal s=x, the output ou... 阅读全文

posted @ 2011-03-28 16:53 yf.x 阅读(2347) 评论(0) 推荐(0)

【笔记】Excel技巧—003 实用的Excel选项设置

摘要：工具 / 选项。启动时不加载任务窗格：选项 / 视图 / 启动任务窗格最近使用的文件列表选项 / 常规 / 最近使用的文件列表新工作簿选项 / 常规 / 新工作簿内的工作表数默认文件位置选项 / 常规 / 默认文件位置用户名选项 / 常规 / 用户名阅读全文

posted @ 2011-03-28 09:43 yf.x 阅读(417) 评论(0) 推荐(0)

【笔记】Excel技巧—002 Excel启动时打开指定工作簿

摘要：工具 / 选项 / 常规 / 启动时打开此目录中的所有文件。将要打开的Excel文件放到XLSTART中。阅读全文

posted @ 2011-03-27 15:56 yf.x 阅读(397) 评论(0) 推荐(0)

【笔记】Excel技巧—001 设置Excel启动

摘要：在快捷方式属性 / 快捷方式 / 目标后加参数 /e 可加快启动速度。加 /s 可以安全模式运行，暂时解决程序故障。阅读全文

posted @ 2011-03-27 15:51 yf.x 阅读(668) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch10

摘要： Chapter 10. Timing and Delays10.6 Exercises1. What type of delay model is used in the following circuit? Write the Verilog description for the module Y. my answer: Distributed Delay. 2. Use the largest delay in the module to convert the circuit to a lumped delay model. Using a lumped delay model, wr 阅读全文

posted @ 2011-03-25 20:13 yf.x 阅读(3302) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch09

摘要： Chapter 9. Useful Modeling Techniques9.7 Exercises1. Using assign and deassign statements, design a positive edge-triggered D-flipflop with asynchronous clear(q=0) and preset (q=1). my answer: 2. Using primitive gates, design a 1-bit full adder FA. Instantiate the full adder inside a stimulus module 阅读全文

posted @ 2011-03-24 17:33 yf.x 阅读(6305) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch08

摘要： Chapter 8. Tasks and Functions8.5 Exercises1. Define a function to calculate the factorial of a 4-bit number. The output is a 32-bit value. Invoke the function by using stimulus and check results. my answer: # Factorial of 4 is 3628800 2. Define a function to multiply two 4-bit numbers a and b. The 阅读全文

posted @ 2011-03-22 10:03 yf.x 阅读(9233) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-III

摘要： 12. Using a case statement, design an 8-function ALU that takes 4-bit inputs a and b and a 3-bit input signal select, and gives a 5-bit output out. The ALU implements the following functions based on a 3-bit input signal select. Ignore any overflow or underflow bits. Select SignalFunction3’b000Out=a 阅读全文

posted @ 2011-03-18 16:08 yf.x 阅读(11232) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-II

摘要： 7. Design a negative edge-triggered D-flipflop(D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg). Design a clock with a period of 10 units and test the D_FF.my 阅读全文

posted @ 2011-03-17 17:00 yf.x 阅读(8827) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-I

摘要： Chapter 7. Behavioral Modeling7.11 Exercises1. Declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement ( Hint: Use the forever loop).my answer:2. Design a clock with time period = 40 and a duty cycle of 25% by using the always and i 阅读全文

posted @ 2011-03-17 11:49 yf.x 阅读(9951) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch06

摘要： Chapter 6. Dataflow Modeling6.7 Exercises1. A full subtractor has three 1-bit inputs x,y,and z(previous borrow) and two 1-bit outputs D(difference) and B(borrow). The logic equations for D and B are as follows: D=x’.y’.z + x’.y.z’ + x.y’.z’ + x.y.z B=x’.y + x’.z + y.z Write the full Verilog descript 阅读全文

posted @ 2011-03-15 20:07 yf.x 阅读(13379) 评论(1) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05

摘要： Chapter 5. Gate-level Modeling5.4 Exercises1. Create your own 2-input Verilog gates called my_or, my_and and my_not from 2-input nand gates. Check the functionality of these gates with a stimulus module. my answer: 2. A 2-input xor gate can be built from my_and, my_or and my_not gates. Construct an 阅读全文

posted @ 2011-03-13 18:45 yf.x 阅读(20753) 评论(0) 推荐(0)

【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch04

摘要： Chapter 4. Modules and Ports4.5 Exercises1. What are the basic components of a module? Which components are mandatory? my answer: 1) Module Name, Port List, Port Declarations, Parameters, Declarations of wires, regs and other variables, Data flow statements, Instantiation of lower level modules, alw 阅读全文

posted @ 2011-03-12 13:21 yf.x 阅读(8064) 评论(0) 推荐(0)