2024年4月16日
Q3c:FSM logic
摘要： 题目网站 module top_module ( input clk, input [2:0] y, input x, output Y0, output z ); assign Y0 = ((~y[2]&y[0])|(y==3'b100))&~x | (~y[2]&~y[0])&x; assign 阅读全文
posted @ 2024-04-16 03:00 江左子固 阅读(133) 评论(0) 推荐(0)
Q3b:FSM
摘要： 题目网站 module top_module ( input clk, input reset, // Synchronous reset input x, output z ); parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010; parameter 阅读全文
posted @ 2024-04-16 02:58 江左子固 阅读(117) 评论(0) 推荐(0)
Q3a:FSM
摘要： Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state 阅读全文
posted @ 2024-04-16 02:56 江左子固 阅读(183) 评论(0) 推荐(0)
Q5b:Serial two's complementer(Moore FSM)
摘要： The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding. module top_module ( input clk, inpu 阅读全文
posted @ 2024-04-16 02:04 江左子固 阅读(223) 评论(2) 推荐(0)
Q5a:Serial two's complementer(Moore FSM)
摘要： You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginnin 阅读全文
posted @ 2024-04-16 02:02 江左子固 阅读(314) 评论(0) 推荐(1)
Q8:Design a Mealy FSM
摘要： Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, t 阅读全文
posted @ 2024-04-16 01:38 江左子固 阅读(127) 评论(0) 推荐(0)
Sequence recognition
摘要： // way1 module top_module( input clk, input reset, // Synchronous reset input in, output disc, output flag, output err); parameter NONE = 4'd0,ONE = 4 阅读全文
posted @ 2024-04-16 00:47 江左子固 阅读(126) 评论(0) 推荐(0)
2024年4月15日
Serial receiver with parity checking
摘要： See also: Serial receiver and datapath We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. 阅读全文
posted @ 2024-04-15 23:44 江左子固 阅读(226) 评论(0) 推荐(0)
Serial receiver and datapath
摘要： See also: Serial receiver Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a da 阅读全文
posted @ 2024-04-15 20:38 江左子固 阅读(105) 评论(0) 推荐(0)
Serial receiver
摘要： In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from 阅读全文
posted @ 2024-04-15 20:32 江左子固 阅读(125) 评论(0) 推荐(0)