随笔分类 -  Hdlbits的Verilog学习 / Circuits / Sequential Logic / Counters

12-hour clock
摘要：Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on 阅读全文
posted @ 2024-04-10 14:37 江左子固 阅读(85) 评论(0) 推荐(0)
4-digit decimal counter
摘要：Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, et 阅读全文
posted @ 2024-04-10 14:29 江左子固 阅读(104) 评论(0) 推荐(0)
Counter 1000
摘要：From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to 阅读全文
posted @ 2024-04-10 14:05 江左子固 阅读(242) 评论(0) 推荐(0)
Counter 1-12
摘要：Design a 1-12 counter with the following inputs and outputs: Reset Synchronous active-high reset that forces the counter to 1 Enable Set high for the 阅读全文
posted @ 2024-04-10 02:19 江左子固 阅读(110) 评论(0) 推荐(0)
Slow decade counter
摘要：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0 阅读全文
posted @ 2024-04-10 02:13 江左子固 阅读(90) 评论(0) 推荐(0)
Decade counter again
摘要：Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1. 题目网站 1 module top_module 阅读全文
posted @ 2024-04-10 02:04 江左子固 阅读(63) 评论(0) 推荐(0)
Decade counter
摘要：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0 阅读全文
posted @ 2024-04-10 01:59 江左子固 阅读(101) 评论(0) 推荐(0)
Four-bit binary counter
摘要：Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the count 阅读全文
posted @ 2024-04-10 01:53 江左子固 阅读(102) 评论(0) 推荐(0)