文章分类 - Hdlbits的Verilog学习 / basic gates
摘要:题目如下: A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector. 代码如下: modu
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摘要:题目如下: A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn o
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摘要:题目如下: Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call
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摘要:题目如下: 代码如下: module top_module (input x, input y, output z); wire za; wire zb; assign za = (x ^ y) & x; assign zb = ~(x ^ y); assign z = (za | zb) ^ (z
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摘要:题目如下: 代码如下: module top_module ( input x, input y, output z ); assign z=~(x^y); endmodule
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摘要:题目如下: Module A is supposed to implement the function z = (x^y) & x. Implement this module. 代码如下: module top_module (input x, input y, output z); assig
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摘要:题目如下: Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should
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摘要:题目如下: In the previous exercises, we used simple logic gates and combinations of several logic gates. These circuits are examples of combinational circ
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摘要:题目如下: The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates. 代码如下: m
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摘要:题目: Ok, let's try building several logic gates at the same time. Build a combinational circuit with two inputs, a and b. There are 7 outputs, each wit
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摘要:题目如图: 代码如下: module top_module ( input in, output out); assign out=in; endmodule 题目如图: 代码如下: module top_module ( output out); assign out=1'b0; endmodul
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摘要:See also the shorter version: Gates and vectors. You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit an
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摘要:You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour: out_both: Each bit of this outpu
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摘要:这道题自己换了一种写法,也是可以运行的,算是过程赋值语句和持续赋值语句的一个小小的对比,也可见《搭建你的数字积木》一书的P56,借鉴了上面的案例。 1 /*module top_module ( 2 input in1, 3 input in2, 4 input in3, 5 output out)
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