文章分类 - Hdlbits的Verilog学习
摘要：题目如下： Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. 代码如下： module top_module( input a, b, sel, output out ); a
阅读全文
摘要：题目如下： A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector. 代码如下： modu
阅读全文
摘要：题目如下： A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn o
阅读全文
摘要：题目如下： Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call
阅读全文
摘要：题目如下： 代码如下： module top_module (input x, input y, output z); wire za; wire zb; assign za = (x ^ y) & x; assign zb = ~(x ^ y); assign z = (za | zb) ^ (z
阅读全文
摘要：题目如下： 代码如下： module top_module ( input x, input y, output z ); assign z=~(x^y); endmodule
阅读全文
摘要：题目如下： Module A is supposed to implement the function z = (x^y) & x. Implement this module. 代码如下： module top_module (input x, input y, output z); assig
阅读全文
摘要：题目如下： Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should
阅读全文
摘要：题目如下： In the previous exercises, we used simple logic gates and combinations of several logic gates. These circuits are examples of combinational circ
阅读全文
摘要：题目如下： The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates. 代码如下： m
阅读全文
摘要：题目： Ok, let's try building several logic gates at the same time. Build a combinational circuit with two inputs, a and b. There are 7 outputs, each wit
阅读全文
摘要：题目如图： 代码如下： module top_module ( input in, output out); assign out=in; endmodule 题目如图： 代码如下： module top_module ( output out); assign out=1'b0; endmodul
阅读全文
摘要：An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. The
阅读全文
摘要：This problem is similar to module. You are given a module named mod_a that has 2 outputs and 4 inputs, in some order. You must connect the 6 ports by
阅读全文
摘要：Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the t
阅读全文
摘要：A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte w
阅读全文
摘要：vectors Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bi
阅读全文
摘要：simple wire module top_module( input in, output out ); assign out=in; endmodule four wires module top_module( input a,b,c, output w,x,y,z ); assign w=
阅读全文
摘要：module top_module( output zero );// Module body starts after semicolon assign zero=0; endmodule
阅读全文
摘要：module top_module( output one ); // Insert your code here assign one = 1; endmodule
阅读全文
浙公网安备 33010602011771号