basics集合

simple wire

module top_module( input in, output out );
	assign out=in;
endmodule

four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
	assign w=a,x=b;
	assign y=b;
    assign z=c;
endmodule 

inverter反相器

module top_module( input in, output out );
	assign out=~in;
endmodule

and gate

module top_module( 
    input a, 
    input b, 
    output out );
assign out=a&b;
endmodule

nor gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a||b); 
endmodule

xnor gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a^b);
endmodule

declaring wires

default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    assign out=(a&b)|(c&d);
    assign out_n=~out;
endmodule

7458 chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	wire w1;
    wire w2;
    wire w3;
    wire w4;
    assign w1=p1a&p1b&p1c;
    assign w2=p2a&p2b;
    assign w3=p2c&p2d;
    assign w4=p1d&p1e&p1f;
    assign p2y=w2|w3;
    assign p1y=w1|w4;
endmodule