摘要: dff.v `timescale 1us/1ns module dff ( input logic clk, input logic [3:0] din, output logic [3:0] qout); always @(posedge clk) begin qout <= din; end e 阅读全文
posted @ 2025-12-26 15:50 大块头 阅读(3) 评论(0) 推荐(0)