AiP74HC83_gate.v 7483 加法器

module AiP74HC83_gate(Sigama, C4, A, B, C0);
output [4:1] Sigama;
output C4;
input [4:1] A;
input [4:1] B;
input C0;

//////////////////////
wire g1_n,p1_n,g2_n,p2_n,g3_n,p3_n,g4_n,p4_n;

nand dut_g1_n (g1_n,A[1],B[1]);
nand dut_g2_n (g2_n,A[2],B[2]);
nand dut_g3_n (g3_n,A[3],B[3]);
nand dut_g4_n (g4_n,A[4],B[4]);

nor dut_p1_n (p1_n,A[1],B[1]);
nor dut_p2_n (p2_n,A[2],B[2]);
nor dut_p3_n (p3_n,A[3],B[3]);
nor dut_p4_n (p4_n,A[4],B[4]);

///////////////////////////////
wire w_c0,c0_n;

not dut_c0_n (c0_n,C0);

not dut_w_c0 (w_c0,c0_n);

wire w_p1;
wire w_3_11;

not dut_w_p1(w_p1,p1_n);
and dut_w_3_11(w_3_11,w_p1,g1_n);
xor dut_Sigama1(Sigama[1],w_3_11,w_c0);

///////////////////////////////

wire w_p2;
wire w_3_22_1,w_3_22_2,w_3_22_3;
wire w_3_22;

not dut_w_p2(w_p2,p2_n);
and dut_w_3_22(w_3_22,w_p2,g2_n);

and dut_w_3_22_1(w_3_22_1,c0_n,g1_n);
buf dut_w_3_22_2(w_3_22_2,p1_n);
nor dut_w_3_22_3(w_3_22_3,w_3_22_2,w_3_22_1);

xor dut_Sigama2(Sigama[2],w_3_22,w_3_22_3);

////////////////////////////////
wire w_p3;
wire w_3_33_1,w_3_33_2,w_3_33_3,w_3_33_4;
wire w_3_33;

not dut_w_p3(w_p3,p3_n);
and dut_w_3_33(w_3_33,w_p3,g3_n);


and dut_w_3_33_1(w_3_33_1,g2_n,p1_n);
and dut_w_3_33_4(w_3_33_4,c0_n,g2_n,g1_n);
buf dut_w_3_33_2(w_3_33_2,p2_n);
nor dut_w_3_33_3(w_3_33_3,w_3_33_4,w_3_33_2,w_3_33_1);

xor dut_Sigama3(Sigama[3],w_3_33,w_3_33_3);

////////////////////////////////
wire w_p4;
wire w_3_44_1,w_3_44_2,w_3_44_3,w_3_44_5,w_3_44_4;

wire w_3_44;

not dut_w_p4(w_p4,p4_n);
and dut_w_3_44(w_3_44,w_p4,g4_n);


and dut_w_3_44_1(w_3_44_1,g3_n,p2_n);
and dut_w_3_44_5(w_3_44_5,g3_n,g2_n,p1_n);
and dut_w_3_44_4(w_3_44_4,c0_n,g3_n,g2_n,g1_n);
buf dut_w_3_44_2(w_3_44_2,p3_n);
nor dut_w_3_44_3(w_3_44_3,w_3_44_5,w_3_44_4,w_3_44_2,w_3_44_1);

xor dut_Sigama4(Sigama[4],w_3_44,w_3_44_3);

////////////////////////////////
wire w_3_5_1,w_3_5_2,w_3_5_3,w_3_5_5,w_3_5_4,w_3_5_6;
buf dut_w_3_5_2(w_3_5_2,p4_n);
and dut_w_3_5_1(w_3_5_1,g4_n,p3_n);
and dut_w_3_5_5(w_3_5_5,g3_n,g4_n,p2_n);
and dut_w_3_5_4(w_3_5_4,p1_n,g4_n,g3_n,g2_n);
and dut_w_3_5_6(w_3_5_6,c0_n,g4_n,g3_n,g2_n,g1_n);
nor dut_C4(C4,w_3_5_6,w_3_5_5,w_3_5_4,w_3_5_2,w_3_5_1);


endmodule

 

`timescale 1ns / 1ps

module AiP74HC83_TB;

// Inputs
reg [4:1] A;
reg [4:1] B;
reg C0;

// Outputs
wire [4:1] Sigama;
wire C4;

// Instantiate the Unit Under Test (UUT)
AiP74HC83_gate uut (
.Sigama(Sigama),
.C4(C4),
.A(A),
.B(B),
.C0(C0)
);

initial begin
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
C0 = 1'b0;
#100; // 等待一段时间观察输出
// 测试所有可能的输入组合
// 测试 0 + 0 + 0
A = 4'b0000;
B = 4'b0000;
C0 = 1'b0;
#100; // 等待一段时间观察输出

// 测试 1 + 0 + 0
A = 4'b0001;
B = 4'b0000;
C0 = 1'b0;
#100;

// 测试 1 + 1 + 0
A = 4'b0001;
B = 4'b0001;
C0 = 1'b0;
#100;

// 测试 15 + 1 + 0
A = 4'b1111;
B = 4'b0001;
C0 = 1'b0;
#100;

// 测试 15 + 1 + 1
A = 4'b1111;
B = 4'b0001;
C0 = 1'b1;
#100;

// 测试 15 + 15 + 1
A = 4'b1111;
B = 4'b1111;
C0 = 1'b1;
#100;

// 结束仿真
$finish;
end

// 监视输出变化
initial begin
$monitor("Time = %t, A = %b, B = %b, C0 = %b, Sigama = %b, C4 = %b",
$time, A, B, C0, Sigama, C4);
end
initial begin
$dumpfile("AiP74HC83_TB.vcd");
//$dumpvars; //无参数，表示设计中的所有信号都将被记录
$dumpvars(0,AiP74HC83_TB);
end
endmodule

 

 

set iverilog_path=C:\iverilog\bin;
set gtkwave_path=C:\iverilog\gtkwave\bin;
set path=%iverilog_path%%gtkwave_path%%path%

set source_module=%1
set testbentch_module=%1_TB

iverilog -o "%testbentch_module%.vvp" -y ./lib/*.v %testbentch_module%.v %source_module%.v
vvp -n "%testbentch_module%.vvp"

set gtkw_file="%testbentch_module%.gtkw"
if exist %gtkw_file% (gtkwave %gtkw_file%) else (gtkwave "%testbentch_module%.vcd")

rem pause