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1.connecting the testbench and the design2.verilog connection review3.systemverilog interfaces4.stimulus timing5.clocking blocks6.timing regions7.prog... 阅读全文
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对于boot a peripherial or module 一般都是配置一系列的寄存器(有可能有时间等方便的写入读出要求)。1.确保寄存器的读写按spec要求完成。<====可以通过波形查看寄存器值是否按要求写入2.模块的启动结束会有标志flag。<====从flag为何失效开始追踪debug3.... 阅读全文
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what is oopterminologyan example classdefault methods for classesstatic attibuteassigment and copyinginheritancepolymorphismwhy oop?1. helps in creati... 阅读全文
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what to randomize?(1) primary input data 1024; data seedthe same seed results in the same random value(5)constraint blocksconstraint constraint_inden... 阅读全文
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How to build and test a module1.test have: generate 、stimulus 、check 、respose2.only one monitor can be active at any time3.$finish VS $finish(2) $fini... 阅读全文