2014年9月18日
systemverilog 之interface/timing region/program
摘要： 1.connecting the testbench and the design2.verilog connection review3.systemverilog interfaces4.stimulus timing5.clocking blocks6.timing regions7.prog... 阅读全文
posted @ 2014-09-18 08:11 CHIPER 阅读(1028) 评论(0) 推荐(0)