FPGA端外设添加到设备树之主系统设备树集成方法（DE25-Nano）

Altera设备树教程骤参考 https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForAgilexSoC  手动加载设备树。

DE25-Nano Linux Image 制作手把手教程：https://github.com/johnnyfan1979/public_doc/blob/main/documentation/DE25_Nano/DE25%20Nano%20Build%20Linux%20image%20from%20scratch.md 

1. 直接在de25_nano_sdmmc/linux-socfpga/arch/arm64/boot/dts/intel路径下将my_de25_nano_overlay.dts内容复制保存为my_de25_nano_overlay.dtsi；

2. 删除第一行的 /dts-v1/; 和 /plugin/;（.dtsi 不需要这些）；

3. 删除 fragment@0 { ... } 整个块，以及 target-path 和 __overlay__ 包装层；

4. 将这些节点直接放到 &soc 引用中，因为主设备树中已有 soc: soc@0 标签。

经过修改的my_de25_nano_overlay.dtsi内容参考如下：

// SPDX-License-Identifier: GPL-2.0
#include "qsys_top.h"

#define AGILEX_LW_H2F_BASE    0x20000000

#define SYSID_QSYS_BASE        (AGILEX_LW_H2F_BASE + AGILEX_HPS_SYS_ID_BASE)
#define LED_PIO_BASE        (AGILEX_LW_H2F_BASE + AGILEX_HPS_LED_PIO_BASE)
#define BUTTON_PIO_BASE        (AGILEX_LW_H2F_BASE + AGILEX_HPS_BUTTON_PIO_BASE)
#define BUTTON_PIO_IRQ        (AGILEX_HPS_BUTTON_PIO_IRQ + 49 - 32)
#define DIPSW_PIO_BASE        (AGILEX_LW_H2F_BASE + AGILEX_HPS_DIPSW_PIO_BASE)
#define DIPSW_PIO_IRQ        (AGILEX_HPS_DIPSW_PIO_IRQ + 49 - 32)

&soc{
            BUTTON_PIO@20010060 {
                compatible = "altr,pio-1.0";
                reg = <BUTTON_PIO_BASE AGILEX_HPS_BUTTON_PIO_SPAN>;
                interrupts = <0 BUTTON_PIO_IRQ 2>;
                altr,ngpio = <AGILEX_HPS_BUTTON_PIO_DATA_WIDTH>;
                altr,interrupt-type = <2>;  /* 2 = IRQ_TYPE_EDGE_FALLING */
                #gpio-cells = <2>;
                gpio-controller;
                status = "okay";
            };
            SYSID_QSYS@20010060 {
                compatible = "altr,sysid-1.0";
                reg = <SYSID_QSYS_BASE AGILEX_HPS_SYS_ID_SPAN>;
            };

            LED_PIO: LED_PIO@20010080 {
                compatible = "altr,pio-1.0";
                reg = <LED_PIO_BASE AGILEX_HPS_LED_PIO_SPAN>;
                altr,ngpio = <AGILEX_HPS_LED_PIO_DATA_WIDTH>;
                #gpio-cells = <2>;
                gpio-controller;
            };

            DIPSW_PIO@20010070 {
                compatible = "altr,pio-1.0";
                reg = <DIPSW_PIO_BASE AGILEX_HPS_DIPSW_PIO_SPAN>;
                interrupts = <0 DIPSW_PIO_IRQ 2>;
                altr,ngpio = <AGILEX_HPS_DIPSW_PIO_DATA_WIDTH>;
                #gpio-cells = <2>;
                gpio-controller;
                altr,interrupt-type = <2>;
                status = "okay";
            };
            leds {
                compatible = "gpio-leds";

                fpga0 {
                    label = "fpga_led0";
                    gpios = <&LED_PIO 0 1>;
                };

                fpga1 {
                    label = "fpga_led1";
                    gpios = <&LED_PIO 1 1>;
                };

                fpga2 {
                    label = "fpga_led2";
                    gpios = <&LED_PIO 2 1>;
                };
                fpga3 {
                    label = "fpga_led3";
                    gpios = <&LED_PIO 3 1>;
                };

                fpga4 {
                    label = "fpga_led4";
                    gpios = <&LED_PIO 4 1>;
                };

                fpga5 {
                    label = "fpga_led5";
                    gpios = <&LED_PIO 5 1>;
                };
                fpga6 {
                    label = "fpga_led6";
                    gpios = <&LED_PIO 6 1>;
                };
            };
    };

 

然后在socfpga_agilex5_de25_nano.dts里面添加一行#include “my_de25_nano_overlay.dtsi”；

 

然后重新编译 socfpga_agilex5_de25_nano.dts。

 

 然后将socfpga_agilex5_de25_nano.dtb文件拷贝到SD卡fat分区：

 

 将SD卡插入DE25-Nano开发板，MSEL[2:0]设置为001，启动板子，可以看到FPGA端外设：

ls /sys -name “*sysid*”

ls /sys/class/leds/

ls/dev/