随笔分类 -  IC/FPGA

摘要：verdi支持混合查看代码，但是需要提前将代码编译为lib vhdl： vhdlcom -lib libname -2000 -f flist.f -- -lib libname 可不写（默认work.lib++） verilog: vericom -lib libname -sv -f flist 阅读全文

摘要：What is Clock Gating? • Register banks disabled during some clock cycles – Typical implementation uses multiplexers – Clock gating cell replaces multi 阅读全文