verilog三段式statemachine脚本

使用示例：python3 test.py -m 14，可以添加参数-p -oh，-p表示参数命名，-oh表示使用onehot编码。

import argparse
import math
def main(args):
    bit = math.ceil(math.log2(args.max))
    if not args.onehot:
        print('reg [{}:0] state;'.format(bit-1))
        print('reg [{}:0] next_state;'.format(bit-1))
    else:
        print('reg [{}:0] state;'.format(args.max-1))
        print('wire [{}:0] next_state;'.format(args.max-1))
    if(args.param):
        for i in range(args.max):
            print('parameter = {}\'d{};'.format(bit,i))
    print('always@(posedge clk or negedge rst)  begin')
    print('    if(!rst)')
    print('        state <= 0;')
    print('    else')
    print('        state <= next_state;')
    print('end')
    if(not args.onehot):
        print('always@(*) begin')
        print('    case(state)')
        for i in range(args.max):
            if(not args.param):
                print('        {}\'d{}: next_state = {}\'d{};'.format(bit, i, bit, i+1))
            else:
                print('        : next_state = ;')
        print('        default: next_state = {}\'d0;'.format(bit))
        print('    endcase')
        print('end')
    else:
        for i in range(args.max):
            print('assign next_state[{}] = state[{}];'.format(i, i-1 if i>0 else i))
if __name__ == '__main__':
    parser = argparse.ArgumentParser()
    parser.add_argument('-m','--max', type=int, default=8, help='num of state for fsm')
    parser.add_argument('-p','--param', action='store_true', help='use param or not')
    parser.add_argument('-oh','--onehot', action='store_true', help='use usehot or not')
    args = parser.parse_args()
    main(args)