并行crc计算 verilog

rtl代码生成网站[http://outputlogic.com/]
并行crc详细代码原理参考论文，parallel_crc_generator_whitepaper
中文解释见网站[https://blog.csdn.net/TMDBYC/article/details/105116043]
uvm的crc代码

function bit [7:0] gen_crc8(bit [7:0] poly, bit [7:0] ori_value , bit [7:0]data_in);
    //poly，多项式系数，用二进制表示，例如01100011表示x^8+x^6+x^5+x+1
    //ori_value，原始值或者中间值
    //data_in，输入值
    bit [7:0] crc8;
    crc8 = ori_value;
    crc8 = crc8 ^ data_in;
    for(int i=0;i<8;i++)begin
        if (crc8[7]!=0)
            crc8 = ( crc8 << 1 ) ^ poly;
        else
            crc8 = crc8 << 1 ;
    crc8 = crc8 & 8'hff;
    end
    return crc8;
endfunction