MPFS250T HSS LOG
HSS: decompressing from eNVM to L2 Scratch ... Passed
[0.41828] wdog_service monitoring [u54_1] [u54_2] [u54_3] [u54_4]
[0.49467] beu_service :: [init] -> [monitoring]
[0.55673] Initializing Mi-V IHC V2
[0.60351] u54 State Change: [Idle] [Idle] [Idle] [Idle]
[0.68467] loop 1 took 6532246 ticks (max 6532246 ticks)
[0.75437] Initializing IPI Queues (3304 bytes @ a02a380)...
[0.739804] loop 3 took 394367627 ticks (max 394367627 ticks)
[0.747252] Initializing PMPs
[0.751357] PolarFire(R) SoC Hart Software Services (HSS) - version 0.99.53-v2026.04.1-16-g19c8c0db
MPFS HAL version 2.3.110 / DDR Driver version 0.4.035 / Mi-V IHC version 2.0.64 / BOARD=mpfs-icicle-kit
(c) Copyright 2017-2025 Microchip FPGA Embedded Systems Solutions.
incorporating OpenSBI - version 1.2
(c) Copyright 2019-2022 Western Digital Corporation.
[0.788022] Build ID: a607a986a314a05acb583031cdd8d35e575ebdbc
[0.795565] Built with the following tools:
- riscv-none-elf-gcc (xPack GNU RISC-V Embedded GCC x86_64) 15.2.0
- GNU ld (xPack GNU RISC-V Embedded GCC x86_64) 2.45
[0.813324] Serial Number:
90e1709f0df1fcfa942271edc26ede9e00000000000000000000000000000000000000000000000000000000000000000000
[0.827264] Segment Configuration:
Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000
Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x30000000
Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x30000000
[0.852184] L2 Cache Configuration:
L2-Scratchpad: 6 ways (768 KiB)
L2-Cache: 4 ways (512 KiB)
L2-LIM: 6 ways (768 KiB)
[0.868034] DESIGNID: system
[0.872339] DESIGNVER: 00.00
[0.876636] BACKLEVEL: 0000
[0.880837] Please ensure that jumpers J34/J43 are correct for 3.3V MMC voltage...
[0.890385] startup_service :: [init] -> [boot]
[0.896496] ipi_poll_service :: [Init] -> [Monitoring]
[0.903275] startup_service :: [boot] -> [idle]
[3.267342] usbdmsc_service :: [Init] -> [Idle]
Press a key to enter CLI, ESC to skip
Timeout in 1 second
..
[4.279465] CLI boot interrupt timeout
[4.284430] loop 279509 took 606580473 ticks (max 606580473 ticks)
[4.292355] Initializing Boot Image ...
[4.297415] Trying to get boot image via MMC ...
[4.303335] Attempting to select eMMC ... Passed
[4.597014] Preparing to copy from MMC ...
[4.602465] GPT signature not as expected
[4.608003] GPT_PartitionIdToLBAOffset() failed - using offset 0
[4.615737] Attempting to read image header (1632 bytes) ...
[4.623349] Copying 25520 bytes to 0x103fc00000
[4.634503] MMC: Boot Image registered ...
[4.639954] Boot image set name: "PolarFire-SoC-HSS::icicle_baremetal"
[4.647974] healthmon_service :: [init] -> [monitoring]
[4.654849] boot_service(u54_1):: BOOT_FLAG_SKIP_OPENSBI found
[4.662392] boot_service(u54_1) :: [Init] -> [SetupPMP]
[4.669266] boot_service(u54_2):: BOOT_FLAG_SKIP_OPENSBI found
[4.676809] boot_service(u54_2) :: [Init] -> [SetupPMP]
>> [4.683970] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[4.691991] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[4.700011] L2:Config:ECCDataFixCount changed since last read (0x1e106)
[4.709464] L2:Config:ECCDataFailCount changed since last read (0x1db53)
[4.719011] u54 State Change: [Booting] [Booting] [Idle] [Idle]
[4.727796] boot_service(u54_1) :: [SetupPMPComplete] -> [ZeroInit]
[4.735816] boot_service(u54_2) :: [SetupPMPComplete] -> [ZeroInit]
[4.744548] boot_service(u54_1) :: [ZeroInit] -> [Download]
[4.751805] boot_service(u54_2) :: [ZeroInit] -> [Download]
[4.759061] boot_service(u54_1)::Processing boot image: "icicle_baremetal"
[4.767463] boot_service(u54_2) :: [Download] -> [Complete]
[4.776586] boot_service(u54_1) :: [Download] -> [OpenSBIInit]
[4.784433] boot_service(u54_1) :: [OpenSBIInit] -> [Wait]
[4.795474] u54 State Change: [Booting] [Running] [Idle] [Idle]
[4.804544] boot_service(u54_1) :: [Wait] -> [Complete]
[4.815299] u54 State Change: [Running] [Running] [Idle] [Idle]
[5.00573] SYSREG:PLL_STATUS_SR not equal to 0x707 (0x303)
[5.08784] SYSREG:MAINTENANCE_INT_SR changed since last read (0xf080)
[5.18046] SYSREG:DLL_STATUS_SR changed since last read (0x80010)
[5.821189] SYSREG:EDAC_SR not equal to 0x0 (0x2800)
[8.824200] SYSREG:EDAC_CNT_CAN0 changed since last read (0x1)
[9.825195] SYSREG:EDAC_CNT_CAN1 changed since last read (0x1)
[10.828837] SYSREG:EDAC_SR not equal to 0x0 (0x3c00)
[13.832803] SYSREG:EDAC_CNT_CAN0 changed since last read (0x3)
[14.833789] SYSREG:EDAC_CNT_CAN1 changed since last read (0x4)
[18.841397] SYSREG:EDAC_CNT_CAN0 changed since last read (0x6)
[19.842384] SYSREG:EDAC_CNT_CAN1 changed since last read (0x6)
[23.850000] SYSREG:EDAC_CNT_CAN0 changed since last read (0x7)
[24.850987] SYSREG:EDAC_CNT_CAN1 changed since last read (0x7)
[28.858603] SYSREG:EDAC_CNT_CAN0 changed since last read (0x9)
[29.859590] SYSREG:EDAC_CNT_CAN1 changed since last read (0x8)
[33.867198] SYSREG:EDAC_CNT_CAN0 changed since last read (0xa)
[34.868193] SYSREG:EDAC_CNT_CAN1 changed since last read (0xa)
[38.875801] SYSREG:EDAC_CNT_CAN0 changed since last read (0xb)
[48.735369] loop 2500000 took 12081 ticks (max 606580473 ticks)
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