libero verilog 模块例化时，信号不存在 默认是 不连接

 

 

 

只有   警告  @W: CS263 :

Port-width mismatch for port o_rx_frame_len. The port definition is 9 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.

 

所以要看 警告 ，排除故障信息