如何在 libero 中 写一个 axi4 slave 总线的 IP核 可以 和 CoreAXI4Interconnect 连接 （三） C代码测试 访问卡死

 

struct s_axi4_reg
{
    uint32_t reg[1024];
};

struct s_axi4_reg *p_axi4_reg;

#define AXI4_REG_BASE ((struct s_axi4_reg *)(0x60000000))

void axi4_reg_test( void )
{
    int i=0;
    for( i=0; i<4; i++ )
    {
        xprintf( "AXI4_REG_BASE reg addr=%d, w_before:%d.\n", i, AXI4_REG_BASE->reg[i] );
        AXI4_REG_BASE->reg[i] = i;
        xprintf( "AXI4_REG_BASE reg addr=%d,w_later:%d.\n", i, AXI4_REG_BASE->reg[i] );
    }
}

 

访问卡死；

在官网论坛查资料：Custom AXI Lite Interface should work? Is there a Microsemi specific AXI protocol?

 

Address Space Warnings and Connection Issues: CoreAXI4DMAController with PolarFire SoC MSS (Libero 2024.2)