spi_slave.v":36:1:36:6|Logic for led_reg does not match a standard flip-flop

 

代码按照下面这么写，编译报错：spi_slave.v":36:1:36:6|Logic for led_reg does not match a standard flip-flop

 

module spi_slave(


    output wire led_1,       // pin_129 / 2.5V
    output wire mod1_gpio_0, // pin_93 / 3.3V

	input wire spi_cs,   // spi_cs / pin_90 / MOD1-4
    input wire spi_clk,  // spi_clk / pin_83 / MOD1-2
    input wire spi_mosi, 
	output wire spi_miso ); // spi_miso / pin_82 / MOD1-7
	
	reg spi_miso_reg;

    reg led_reg = 1'b0;
    
	always @( posedge spi_clk or negedge spi_cs) begin
		case({spi_cs,spi_clk})
            2'b00: led_reg <= ~led_reg; // signal spi_cs high ---> low
            2'b01: led_reg <= ~led_reg; // signal spi_clk low ---> high
            default: led_reg <= 1'b1;   // what signal?
        endcase
	end
		
	assign spi_miso = spi_miso_reg;

    assign led_1 = led_reg;
    assign mod1_gpio_0 = led_reg;

endmodule

 这样写代码不行！！！