笔记No. 2 Avalon-ST讨论[BBS版]

1. How to store data from A/D onto DDR2 SDRAM and stream out

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Q: I submitted a question before on how to get 128k output from SignalTap. I just found out that I wouldn't be able to with external ram installed as SignalTap can only use internal RAM. Is there some way I can get a signal from A/D stored onto a DDR2 SDRAM, then stream the data out via a cable like USB or Ethernet? I'm using a Stratix III DSP Development Board.

A: You can stream data from an ADC to memory. You need to calculate the data rates though. First, create an SOPC/Qsys system containing an Avalon-MM master (eg. the verification IP suite BFM), DDR memory controller and a DMA controller, and determine the maximum sustained transfer rate to your DDR memory. This rate determines the maximum sampling rate you will be able to run your ADC.

You can define your ADC as an Avalon-ST streaming source component, and then add that to SOPC/Qsys along with an SGDMA component, and using that you can DMA from the Avalon-ST component to the DDR memory.

 

2. Passing channel to Avalon-ST demultiplexer

Q: I am trying to build a component, which will be connected to Avalon-ST demultiplexer. Since the data has to be switched between inputs, I've added aso_channel signal. The SOPC builder complains, that source max channel is 0 and sink has max channel 1, so I've added a generic MAX_CHANNEL : integer := 1, but this didn't help. How can I pass the parameter to SOPC builder?

A1: i don't completely understand what your system looks like, but it sounds like you may want to drive the channel input yourself? SOPC Builder wants to wire the channel I/O from one ST block to the next. if both blocks do not have the channel signal you'll have to look at making your own demux block with the select line defined as a conduit, or at channel adapters (though i'm not sure how the select line would work in this case)

A2: i think max channel is derived from the width (or presence) of a channel signal on an ST block, so it has to be an actual port to your module

Q: Well, since I use demultiplexer, it has one IN and two OUT signals. In this case, I want to switch between those out lines, so I've made my own sopc component, which has channel (output) signal. This component is connected to multiplexer input.

A: The input to the demux should have a channel signal so that the demux and de-interleave the data to various outputs. For example if you sent a stream of data like this:

Code:

Data      Channel
1            0
3            0
5            1
8            0

You should expect to see 1, 3, 8 come out of the first demux output and 5 come out of the second demux output. If you are looking for a demux that can take a channel-less input stream and route it to whatever port you want take a look at the Qsys tutorial, there is an IP core in there that takes a stream of data in and routes it to output A or B depending on which output you select through the slave port. I forget what I called it but it's something like "one_to_two_st_demux".

Q:

Quote:

Originally Posted by BadOmen

The input to the demux should have a channel signal so that the demux and de-interleave the data to various outputs. For example if you sent a stream of data like this:

Code:

Data      Channel
1            0
3            0
5            1
8            0

Everything is correct, when I change the channel signal, the data goes as required. However, I use demultiplexer with 16 channels output (channel is 4 bits wide). My core which controls the channels also has channel signal 4 bits wide. Everything here is fine, but I get error for max channel parameter, so I have to use channel adapter:

Code:

The source's max channel is 0, while the sink's is 15. Consider inserting...

If I could define that max channel parameter in my core, I could connect the core directly to demultiplexer without using a channel adapter.

It's a very simple solution, but I don't know how to set that internal parameter in VHDL. It should be generic? Which type?

A: Take a look at the tcl file for the read master of the modular SGDMA up on the alterawiki, it tunes max channel on the fly.

Q: Oh, this parameter is used to set in tcl, not the hdl file... Thanks, seems like everything is ok now.

A: Yep that's correct. It's present in .tcl instead of being directly derived from the width of the channel signal so that you can limit the number of channels. Otherwise you would be stuck with 2, 4, 8, 16, 32, 64, etc... channels.