随笔分类 -  Hdlbits的Verilog学习 / Circuits / Building Larger Circuits

FSM:One-hot logic equations
摘要：题目网站 module top_module( input d, input done_counting, input ack, input [9:0] state, // 10-bit one-hot current state 这个是独热码输入现态 output B3_next, output 阅读全文
posted @ 2024-04-16 04:05 江左子固 阅读(107) 评论(0) 推荐(0)
The complete timer
摘要：题目网站 module top_module ( input clk, input reset, // Synchronous reset input data, output [3:0] count, output counting, output done, input ack ); reg [ 阅读全文
posted @ 2024-04-16 04:02 江左子固 阅读(204) 评论(0) 推荐(0)
FSM:The complete FSM
摘要：题目网站 module top_module ( input clk, input reset, // Synchronous reset input data, output shift_ena, output counting, input done_counting, output done, 阅读全文
posted @ 2024-04-16 03:59 江左子固 阅读(120) 评论(0) 推荐(0)
FSM:Enable shift register
摘要：module top_module ( input clk, input reset, // Synchronous reset output shift_ena); parameter IDLE = 2'd0, ENA = 2'd1, STOP = 2'd2; reg [1:0] current_ 阅读全文
posted @ 2024-04-16 03:51 江左子固 阅读(80) 评论(0) 推荐(0)
FSM:Sequence 1101 recognizer
摘要：题目网站 module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter IDLE = 3'd0, S1 = 3'd1, S2 = 3'd2; 阅读全文
posted @ 2024-04-16 03:44 江左子固 阅读(86) 评论(0) 推荐(0)
4-bit shift register and down counter
摘要：This is the first component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for th 阅读全文
posted @ 2024-04-16 03:40 江左子固 阅读(156) 评论(0) 推荐(0)
Counter with period 1000
摘要：Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0. 阅读全文
posted @ 2024-04-16 03:38 江左子固 阅读(86) 评论(0) 推荐(0)