detect both edges

题目如下：

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

代码如下：

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0]temp=0;
    always@(posedge clk)begin
    	temp<=in;
        anyedge<=~temp&in|temp&~in;
    end
endmodule

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0]a;
    always@(posedge clk)begin
        a<=in;
        anyedge<=a^in;
    end
endmodule

这两个都是可以的，第二种算是第一种的简化