Serial receiver

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter [3:0] START = 4'd0;
parameter [3:0] ONE = 4'd1;
parameter [3:0] TWO = 4'd2;
parameter [3:0] THREE = 4'd3;
parameter [3:0] FOUR = 4'd4;
parameter [3:0] FIVE = 4'd5;
parameter [3:0] SIX = 4'd6;
parameter [3:0] SEVEN = 4'd7;
parameter [3:0] EIGHT = 4'd8;
parameter [3:0] STOP = 4'd9;
parameter [3:0] IDLE = 4'd10;
parameter [3:0] WAIT = 4'd11;

reg [3:0] state,next_state;

always @(*)begin
    case(state)
        START:begin
            next_state = ONE;
        end
        ONE:begin
            next_state = TWO;
        end
        TWO:begin
            next_state = THREE;
        end
        THREE:begin
            next_state = FOUR;
        end
        FOUR:begin
            next_state = FIVE;
        end
        FIVE:begin
            next_state = SIX;
        end
        SIX:begin
            next_state = SEVEN;
        end
        SEVEN:begin
            next_state = EIGHT;
        end
        EIGHT:begin
            if(in)begin
                next_state = STOP;
            end
            else begin
                next_state = WAIT;
            end
        end
        STOP:begin
            if(in)begin
                next_state = IDLE;
            end
            else begin
                next_state = START;
            end
        end
        WAIT:begin
            if(in)begin
                next_state = IDLE;
            end
            else begin
                next_state = WAIT;
            end
        end
        IDLE:begin
            if(~in)begin
                next_state = START;
            end
            else begin
                next_state = IDLE;
            end
        end
    endcase
end

always @(posedge clk)begin
    if(reset)begin
        state <= IDLE;
    end
    else begin
        state <= next_state;
    end
end

assign done = (state == STOP);

endmodule