Simple FSM1(synchronous reset)

Fsm1s - HDLBits (01xz.net)

 1 module top_module(
 2     input clk,
 3     input reset,    // Asynchronous reset to state B
 4     input in,
 5     output out);//  
 6 
 7     parameter A=0, B=1; 
 8     reg state, next_state;
 9 
10     always @(*) begin    // This is a combinational always block
11         case(state)
12             A:begin   
13                 if(in == 1'b1)begin
14                     next_state = A;
15                 end
16                 else begin
17                     next_state = B;
18                 end
19             end
20             B:begin
21                 if(in == 1'b1)begin
22                     next_state = B;
23                 end
24                 else begin
25                     next_state = A;
26                 end
27             end
28         endcase
29     end
30 
31     always @(posedge clk) begin    // This is a sequential always block
32         if(reset)begin
33             state <= B;
34         end
35         else begin
36             state <= next_state;
37         end
38     end
39 
40     // Output logic
41     assign out = (state == B);
42 
43 endmodule

 

posted @ 2023-04-27 18:37  江左子固  阅读(22)  评论(0)    收藏  举报