Simple FSM1(asynchronous reset)

Fsm1 - HDLBits (01xz.net)

 1 module top_module(
 2     input clk,
 3     input areset,    // Asynchronous reset to state B
 4     input in,
 5     output out);//  
 6 
 7     parameter A=0, B=1; 
 8     reg state, next_state;
 9 
10     always @(*) begin    // This is a combinational always block
11         // State transition logic
12         case(state)
13             A:begin
14                 if(in == 1'b1)begin
15                     next_state = A;
16                 end
17                 else begin
18                     next_state = B;
19                 end
20             end
21             B:begin
22                 if(in == 1'b1)begin
23                     next_state = B;
24                 end
25                 else begin
26                     next_state = A;
27                 end
28             end
29         endcase
30     end
31 
32     always @(posedge clk, posedge areset) begin    // This is a sequential always block
33         // State flip-flops with asynchronous reset
34         if(areset)begin
35             state <= B;
36         end
37         else begin
38             state <= next_state;
39         end
40     end
41 
42     // Output logic
43     // assign out = (state == ...);
44     assign out = (state == B);   //这个是为什么？在图中并没有说吧
45 endmodule

 再写：

assign out = (state == B);有写，直接根据图中的out来判断
posted @ 2023-04-27 15:45  江左子固  阅读(23)  评论(0)    收藏  举报