create circuit from truth table

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

Exams/ece241 2013 q7 - HDLBits (01xz.net)

 

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
always @(posedge clk) begin
        case({j,k})
            2'b00:Q<=Q;
            2'b01:Q<=1'b0;
            2'b10:Q<=1'b1;
            2'b11:Q<=~Q;
        endcase
    end
endmodule

 

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    always@(posedge clk)begin
        Q<=(j*(~Q))|((~k)*Q);
    end
endmodule