dffs and gates

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

Exams/ece241 2014 q4 - HDLBits (01xz.net)

 

module top_module (
    input clk,
    input x,
    output z
); 
reg Q1,Q2,Q3;
    always @(posedge clk) begin
        Q1 <= (x ^ Q1);
        Q2 <= (x & ~Q2);
        Q3 <= (x | ~Q3);
    end
    assign z = ~(Q1|Q2|Q3);

endmodule

module top_module (
input clk,
input x,
output z
);
wire q1,q2,q3;
wire d1,d2,d3;
assign d1=x^q1;
assign d2=x&(~q2);
assign d3=x|(~q3);
assign z=~(q1|q2|q3);
always@(posedge clk)begin
q1<=d1;
q2<=d2;
q3<=d3;
end
endmodule