dff with reset

同步复位，也可见《数字积木》一书P85

Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

Dff8p - HDLBits (01xz.net)

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    /*always @(posedge clk)
        begin
            if(reset)
                q<=8'd0;   //应该是这个地方写错了，换成8'h0x34
            else 
                q<=d;
        end*/
        always @(posedge clk) begin
        if(!reset)
            q <= d;
        else
            q <=8'd0;   //这两个方法都没有运行成功，也不知道是因为什么
    end
endmodule

 使用posedge areset时，只能使用if(areset)首先进行判断而不能用if(!areset)，否则会报错。

异步Asynchronous：清零端与时钟无关，复位取决于clr（rst）的上升沿，always @(posedge clk or negedge rst)
同步Synchronous：复位的动作与时钟同步，复位取决于时钟的上升沿并且clr在高位，always @(posedege clk)

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
 always @(negedge clk) begin
        if(!reset)
            q <= d;
        else
            q <= 8'h0x34;   //这个是可以运行的
    end
endmodule

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
 always @(negedge clk) begin
        if(reset)
            q <= 8'h0x34;
        else
     q <= d;//这个是可以运行的
    end
endmodule