if statement

This is equivalent to using a continuous assignment with a conditional operator:

assign out = (condition) ? x : y;
However, the procedural if statement provides a new way to make mistakes. The circuit is combinational only if out is always assigned a value.

Always if - HDLBits (01xz.net)

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    always @(*)begin
        if(sel_b1&&sel_b2) begin
            out_always<=b;
        end
        else begin
            out_always<=a;
        end
    end   //很奇怪，康华光书上并没有写end，是因为书上的例子只有always这一个模块吧
    
    assign out_assign=(sel_b1&&sel_b2)?b:a;

endmodule

 再写：

不知道为什么当时很喜欢在组合里面用非阻塞……写的有点丑