carry-select adder

One drawback of the ripple carry adder (See previous exercise) is that the delay for an adder to compute the carry out (from the carry-in, in the worst case) is fairly slow, and the second-stage adder cannot begin computing its carry-out until the first-stage adder has finished. This makes the adder slow. One improvement is a carry-select adder, shown below. The first-stage adder is the same as before, but we duplicate the second-stage adder, one assuming carry-in=0 and one assuming carry-in=1, then using a fast 2-to-1 multiplexer to select which result happened to be correct.

In this exercise, you are provided with the same module as the previous exercise, which adds two 16-bit numbers with carry-in and produces a carry-out and 16-bit sum. You must instantiate three of these to build the carry-select adder, using your own 16-bit 2-to-1 multiplexer. add16

Connect the modules together as shown in the diagram below. The provided module has the following declaration: add16

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Module cseladd - HDLBits (01xz.net)

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout_sel,cout1,cout2;
    wire [31:0]sum1,sum2;
    add16 add16_lower(a[15:0],b[15:0],1'b0,sum[15:0],cout_sel);
    add16 add16_up1(a[31:16],b[31:16],1'b0,sum1[31:16],cout1);
    add16 add16_up2(a[31:16],b[31:16],1'b1,sum2[31:16],cout2);
    assign sum[31:16]=cout_sel?sum2[31:16]:sum1[31:16];/*此处总报错
    Error (12014): Net "sum[31]", which fans out to "sum[31]", 
    cannot be assigned more than one value File:
    /home/h/work/hdlbits.10367748/top_module.v Line: 5
    因为上两行忘记添加1、2了，故报错*/
endmodule

总是报错，问题还没解决，参考了这个代码(29条消息) HDLBits 系列（2）——Verilog Language（Modules: Hierarchy、Procedures）_Bronceyang131的博客-CSDN博客

问题已经解决，自己粗心导致，现在是可以运行的