connecting ports by position

This problem is similar to the previous one (module). You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your top-level module's ports out1, out2, a, b, c, and d, in that order.

You are given the following module:

module mod_a ( output, output, input, input, input, input );

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    /*mod_a instance2(
        .out1(out1),
        .out2(out2),
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d));*/
    mod_a mod_a_inst(out1,out2,a,b,c,d);   //这个是可以运行的，但是与上面注释内有和不同呢？
endmodule

(29条消息) HDLBits 系列（2）——Verilog Language（Modules: Hierarchy、Procedures）_Bronceyang131的博客-CSDN博客 此博客中对于此题的解释，在注释内的写法与我类似，但是不能运行，对于我编写的，报错如下，我还要再想一想：

Error (12002): Port "in1" does not exist in macrofunction "instance2" File: /home/h/work/hdlbits.10364666/top_module.v Line: 15

再写：
这在注释里写的当然是不能运行的，因为这一题就是要按位置引用，并且没有给出可以按名称引用的子模块，所以当然引用不了，想按名称，题目都没条件当然没法写，总是错