verilog format 工具

https://github.com/chipsalliance/verible

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/08/31 19:09:48
// Design Name: 
// Module Name: user_led
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module user_led (
    i_clk,
    i_rst_n,
    led
);

  input i_clk;
  input i_rst_n;
  output [2:0] led;

  reg [25:0] cnt;
  reg [ 2:0] led_r;
  reg [ 3:0] count;


  //design_1_wrapper u1  //将PS部分50M的时钟例化到PL中
  //       (
  //       .FCLK_CLK0(i_clk)
  //        );

  always @(posedge i_clk or negedge i_rst_n)  //1s的计数led有点慢这里用的是0.5s计数
    if (i_rst_n == 1'b0) cnt <= 26'd0;
    else if (cnt == 26'd24999999) cnt <= 26'd0;
    else cnt <= cnt + 1'b1;

  always @(posedge i_clk or negedge i_rst_n)
    if (i_rst_n == 1'b0) count <= 4'd0;
    else if (count == 4'd3 && cnt == 26'd24999999) count <= 4'd0;
    else if (cnt == 26'd24999999) count <= count + 1'b1;

  always @(posedge i_clk or negedge i_rst_n)  //注意三色灯是共阳极接法
    if (i_rst_n == 1'b0) led_r <= 3'b111;
    else
      case (count)
        4'd0: led_r <= 3'b110;
        4'd1: led_r <= 3'b101;
        4'd2: led_r <= 3'b011;
        4'd3: led_r <= 3'b000;
        default: led_r <= 3'b111;
      endcase

  assign led = led_r;

endmodule

verible-verilog-format --inplace .\user_led.v