2013_q2bfsm

module top_module (
    input  clk,
    input  resetn,  // active-low synchronous reset
    input  x,
    input  y,
    output f,
    output g
);
  parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5, G = 6, H = 7, ON = 14, OFF = 15;
  reg [3:0] state, nstate;
  assign f = state == B;
  assign g = state == F || state == G ||state == ON;

  always @(*) begin
    case (state)
      A:       nstate = B;
      B:       nstate = C;
      C:       nstate = x ? D : C;
      D:       nstate = x ? D : E;
      E:       nstate = x ? F : C;
      F:       nstate = y ? ON : G;  //g
      G:       nstate = y ? ON : H;
      H:       nstate = OFF;
      ON:      nstate = ON;
      OFF:     nstate = OFF;
      default: nstate = A;
    endcase
  end
  always @(posedge clk) begin
    if (~resetn) begin
      state = A;
    end else begin
      state = nstate;
    end
  end

endmodule