2014_q3fsm

module top_module (
    input clk,
    input reset,  // Synchronous reset
    input s,
    input w,
    output reg z
);
  reg state, nstate;
  reg [3:0] sw, nsw;

  always @(*)
    case (state)
      0: nstate = s ? 1 : 0;
      1: nstate = 1;
    endcase
  always @(posedge clk)
    if (reset) state <= 0;
    else state <= nstate;

  always @(*) begin
    case (sw)
      0: nsw = w ? 1 : 2;  //1
      1: nsw = w ? 3 : 4;  //2      1
      2: nsw = w ? 4 : 5;  //2      0
      3: nsw = 0;  //3      2
      4: nsw = 0;  //3      1
      5: nsw = 0;  //3      0
    endcase
  end
  always @(posedge clk)
    if (reset | ~state) sw = 0;
    else sw = nsw;

  always @(posedge clk) begin
    if (reset) z = 0;
    else begin
      z = (sw == 3 && w == 0) || (sw == 4 && w == 1);
    end
  end

endmodule