Lemmings4 

 1 module Lemmings4 (
 2     input clk,
 3     input areset,  // Freshly brainwashed Lemmings walk left.
 4     input bump_left,
 5     input bump_right,
 6     input ground,
 7     input dig,
 8     output walk_left,
 9     output walk_right,
10     output aaah,
11     output digging
12 );
13   parameter LEFT = 0, RIGHT = 1, FALL_L = 2, FALL_R = 3, DIG_L = 4, DIG_R = 5, SPLAT = 7;
14   reg [2:0] state, next_state;
15   reg [4:0] counter;
16 
17   always @(*) begin
18     // State transition logic
19     case (state)
20       LEFT:   next_state = ground ? (dig ? DIG_L : (bump_left ? RIGHT : LEFT)) : FALL_L;
21       RIGHT:  next_state = ground ? (dig ? DIG_R : (bump_right ? LEFT : RIGHT)) : FALL_R;
22       FALL_L: next_state = ground ? LEFT : FALL_L;
23       FALL_R: next_state = ground ? RIGHT : FALL_R;
24       DIG_L:  next_state = ground ? DIG_L : FALL_L;
25       DIG_R:  next_state = ground ? DIG_R : FALL_R;
26       SPLAT:  next_state = SPLAT;
27 
28       default: next_state = LEFT;
29     endcase
30   end
31 
32   always @(posedge clk, posedge areset) begin
33     // State flip-flops with asynchronous reset
34     if (areset) begin
35       state <= LEFT;
36       counter = 0;
37     end else begin
38       state <= ((counter > 20) & ground) ? SPLAT : next_state;
39       if (next_state == FALL_L | next_state == FALL_R) begin
40         counter = counter > 20 ? counter : counter + 1;
41       end else begin
42         counter = 0;
43       end
44     end
45   end
46 
47   // Output logic
48   assign walk_left = (state == LEFT) & (state != SPLAT);
49   assign walk_right = (state == RIGHT) & (state != SPLAT);
50   assign aaah = (state == FALL_L | state == FALL_R) & (state != SPLAT);
51   assign digging = (state == DIG_L | state == DIG_R) & (state != SPLAT);
52 endmodule

 

posted @ 2023-08-29 17:15  deweii  阅读(71)  评论(0)    收藏  举报