Exams_ece241_2013_q4 

 1 module Exams_ece241_2013_q4 (
 2     input clk,
 3     input reset,
 4     input [3:1] s,
 5     output fr3,
 6     output fr2,
 7     output fr1,
 8     output dfr
 9 );
10 
11   parameter A = 3'b000, B = 3'b001, C = 3'b011, D = 3'b111;
12   reg [2:0] state, last_state;
13 
14   always @(posedge clk) begin
15     if (reset) begin
16       state <= A;
17       last_state <= A;
18     end else begin
19       state <= s;
20       last_state <= state;
21     end
22   end
23 
24   assign {fr1, fr2, fr3} = ~state;
25   assign dfr = (dfr ? state <= last_state : state < last_state) | (state == A);
26 
27 endmodule

 

posted @ 2023-08-29 14:43  deweii  阅读(35)  评论(0)    收藏  举报