实验程序

module lbwyyds2(clk,rst_n,dout);
input clk,rst_n;
output [7:0] dout;
reg[7:0] address;
reg rden;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)rden<=0;
else rden<=1;
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)address<=0;
else address<=address+1;
end
lbwyyds3 u1(.address(address),.clock(clk),.rden(rden),.q(dout));
endmodule