Verilog 进击之路 - 夯实基础第三节之verilog主力团二

Verilog 进击之路 - 夯实基础第三节之verilog主力团二

 

Behavior model

Initial只执行一次，且多个initial之间是并行执行的。一般用来initialization, monitoring, waveforms，或者其他在整个仿真进程中只执行一次的process.

       1 Variables can be initialized by declared，来代替initial。比如 reg clock =0;

       2 Combined port/data declared

　　　　module addr(a,b,ci,sum,co);

　　　　　　output reg [7:0] sum =0;

　　　　　　output reg co =0;

　　　　　　input [7:0] a, b;

　　　　　　input ci;

              endmodule

       always statement start time 0 并持续的执行，用来模拟一个持续active的digital circuit. 比如 clock generator 从上电开始就active，所以可以使用always.只能被an interrupt $stop or power off $finish 中断。

Timing control

       三种timing control : delay-based timing control, event-based timing control, level sensitive timing control.

       #10 #latency #(4:5:6) a =b;

　　X = #10 y;

　　@(clock)

　　@(posedge clock) q=d

　　q = @(posedge clock)d

　　event receive_data;

　　always @(posedge clock) begin

    　　   if(last_data_package)

                     ->receive_data;  

　　end

 

always(posedge receive_data) begin

end