EECS 151. Introduction to Digital Design and Integrated Circuits
EECS 151. Introduction to Digital Design and Integrated Circuits
Catalog Description: An introduction to digital and system design. The material provides a top-down view of the principles, components, and methodologies for large scale digital system design. The underlying CMOS devices and manufacturing technologies are introduced, but quickly abstracted to higher-levels to focus the class on design of larger digital modules for both FPGAs (field programmable gate arrays) and ASICs (application specific integrated circuits). The class includes extensive use of industrial grade design automation and verification tools for assignments, labs and projects. The class has two lab options: ASIC Lab (EECS 151LA) and FPGA Lab (EECS 151LB). Students must enroll in at least one of the labs concurrently with the class.
Units: 3
Related Areas:
Course Objectives: The Verilog hardware description language is introduced and used. Basic digital system design concepts, Boolean operations/combinational logic, sequential elements and finite-state-machines, are described. Design of larger building blocks such as arithmetic units, interconnection networks, input/output units, as well as memory design (SRAM, Caches, FIFOs) and integration are also covered. Parallelism, pipelining and other micro-architectural optimizations are introduced. A number of physical design issues visible at the architecture level are covered as well, such as interconnects, power, and reliability.
Prerequisites: EECS 16A and EECS 16B.
Credit Restrictions: Students must enroll concurrently in at least one the lab flavors EECS151LA or EECS151LB. Students wishing to take a second lab flavor next term can sign-up only for that Lab section and receive a Letter grade. The pre-requisite for “Lab-only” enrollment that term will be EECS151 from previous terms.
Formats:
Fall: 3.0 hours of lecture and 1.0 hours of discussion per week
Grading Basis: letter
Final Exam Status: Written final exam conducted during the scheduled final exam period
Class Schedule (Spring 2025):
EECS 151/251A – TuTh 09:30-10:59, Soda 306 – John Wawrzynek
Class Notes
Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.
*To enroll in this class:
1) Select the lecture and discussion time
2) Through a seprate enrollment, select either 151/251LA or 151/251LB*
YOU WILL BE DROPPED FROM THE LECTURE IF YOU DO NOT ADD A LAB.
NO TIME CONFLICTS WITH LECTURE
*To enroll in this class, select the lecture and the 999 (placeholder) discussion section. Assignment to the actual sections will be managed by teaching staff.*
**Enrollment Permission seats are reserved for internal programs and are not open. Please DO NOT email the instructor or scheduling to request a seat**
Class Schedule (Fall 2025):
EECS 151/251A – TuTh 09:30-10:59, Mulford 159 – John Wawrzynek
Class Notes
Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.
*To enroll in this class:
1) Select the lecture and discussion time
2) Through a seprate enrollment, select either 151/251LA or 151/251LB*
YOU WILL BE DROPPED FROM THE LECTURE IF YOU DO NOT ADD A LAB.
NO TIME CONFLICTS WITH LECTURE
*To enroll in this class, select the lecture and the 999 (placeholder) discussion section. Assignment to the actual sections will be managed by teaching staff.*
**Enrollment Permission seats are reserved for internal programs and are not open. Please DO NOT email the instructor or scheduling to request a seat**
EECS151 数字设计与集成电路导论
目录描述：数字和系统设计介绍。该材料自上而下地介绍了大规模数字系统设计的原理、组件和方法。介绍了底层的CMOS器件和制造技术，但很快被抽象到更高的层次，将课程重点放在FPGA（现场可编程门阵列）和ASIC（专用集成电路）的更大数字模块的设计上。该课程包括在作业、实验室和项目中广泛使用工业级设计自动化和验证工具。该课程有两个实验室选项：ASIC实验室（EECS 151LA）和FPGA实验室（EECS 151LB）。学生必须在课堂上同时注册至少一个实验室。
单位：3
相关领域：
计算机体系结构与工程（ARC）
课程目标：介绍并使用Verilog硬件描述语言。描述了基本的数字系统设计概念、布尔运算/组合逻辑、时序元件和有限状态机。还涵盖了更大的构建块的设计，如算术单元、互连网络、输入/输出单元，以及存储器设计（SRAM、缓存、FIFO）和集成。介绍了并行性、流水线和其他微架构优化。还涵盖了架构级别可见的许多物理设计问题，如互连、电源和可靠性。
先决条件：EECS 16A和EECS 16B。
学分限制：学生必须同时注册至少一个实验室口味的EECS151LA或EECS151LB。希望下学期参加第二次实验的学生只能报名参加该实验部分，并获得Letter成绩。该学期“仅限实验室”注册的先决条件是之前学期的EECS151。
格式：
秋季：每周3.0小时的讲座和1.0小时的讨论
评分依据：字母
期末考试状态：在预定的期末考试期间进行的笔试
课程表（2025年春季）：
EECS 151/251A–星期五09:30-10:59，苏打水306–约翰·沃兹尼克
课堂笔记
第一阶段和第二阶段的席位向EECS、CS和非EECS COE专业开放。其余座位在调整期间开放。
*要注册此课程：
1） 选择讲座和讨论时间
2） 通过单独注册，选择151/251LA或151/251LB*
如果你不增加一个实验室，你将被从讲座中除名。
与讲座没有时间冲突
*要注册此课程，请选择讲座和999（占位符）讨论部分。实际部门的分配将由教职员工管理*
**注册权限席位保留给内部项目，不开放。请不要给讲师或日程安排发电子邮件要求座位**
课程表（2025年秋季）：
EECS 151/251A–周日09:30-10:59，马尔福德159–约翰·沃兹内克
课堂笔记
第一阶段和第二阶段的席位向EECS、CS和非EECS COE专业开放。其余座位在调整期间开放。
*要注册此课程：
1） 选择讲座和讨论时间
2） 通过单独注册，选择151/251LA或151/251LB*
如果你不增加一个实验室，你将被从讲座中除名。
与讲座没有时间冲突
*要注册此课程，请选择讲座和999（占位符）讨论部分。实际部门的分配将由教职员工管理*
**注册权限席位保留给内部项目，不开放。请不要给讲师或日程安排发电子邮件要求座位**
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