xilinx a7 在线升级

// STARTUPE2: STARTUP Block
STARTUPE2 #(
  .PROG_USR      ("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
  .SIM_CCLK_FREQ (0.0)       // Set the Configuration Clock Frequency(ns) for simulation.
)STARTUPE2_inst (
  .CFGCLK(),             // 1-bit output: Configuration main clock output
  .CFGMCLK(),            // 1-bit output: Configuration internal oscillator clock output
  .EOS(),                // 1-bit output: Active high output signal indicating the End Of Startup.
  .PREQ(),               // 1-bit output: PROGRAM request to fabric output
  .CLK(1'b0),            // 1-bit input: User start-up clock input
  .GSR(1'b0),            // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
  .GTS(1'b0),            // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
  .KEYCLEARB(1'b0),      // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
  .PACK(1'b0),           // 1-bit input: PROGRAM acknowledge input
  .USRCCLKO(usr_cclk),   // 1-bit input: User CCLK input
  .USRCCLKTS(1'b0),      // 1-bit input: User CCLK 3-state enable input   (must also be driven Low to ensure the CCLK output---add by rudy)
      .USRDONEO(1'b1),       // 1-bit input: User DONE pin output control
  .USRDONETS(1'b0)       // 1-bit input: User DONE 3-state enable output);

实际应用的时候，usr_cclk为外部输入时钟信号，可输入一个clk27M180(180反向)的时钟，然后spi接口用的spi时钟为clk27m