AM335x的双网口+AR8035

环境

AM335x的双网口 phy是AR8035

内核版本

6.1

硬件描述

两个phy芯片都为AR8035，共用同一个MDIO通讯，一个phy在核心板上，另一个phy在底板上，RJ45的两个网口在底板上。

问题描述

有双网口节点，但是ping不通，TX，RX时钟也是正常的，使用ping操作时抓包工具Wireshark抓包发现MAC包可以发出来，回应之后就没有下一步了。ifconfig命令的包统计是RX packets为0，下图指出位置，不是问题截图。

alt text

分析过程

以上情况说明是网口MAC和phy之间的信号接收问题，千兆是在时钟的上/下边沿均采样数据，有延时设置的，设置了tx clock delay 2.4ns的延时，其中离CPU远的那个phy正常了，在核心板上的phy还是这样问题，于是想改下RX引脚状态试下，设置了这个phy对应的RX引脚状态由PIN_OUTPUT_PULLDOWN改为PIN_INPUT_PULLUP就可以了。可能是phy离CPU的远近对信号有影响导致的。

解决

phy寄存器初始化配置：

static int at803x_config_init(struct phy_device *phydev)
{
	int val;
	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(phydev, 0xd, 0x7);
	phy_write(phydev, 0xe, 0x8016);
	phy_write(phydev, 0xd, 0x4007);
	val = phy_read(phydev, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, 0xe, val);

	phy_write(phydev, 0x1d, 0x5);
	val = phy_read(phydev, 0x1e);
	val |= 0x0100;
	phy_write(phydev, 0x1e, val);

	// if (phydev->mdio.addr == 1) {
	// 	phy_write(phydev, 0x1d, 0x0);
	// 	val = phy_read(phydev, 0x1e);
	// 	val &= ~(1 << 14);
	// 	phy_write(phydev, 0x1e, val);
	// 	printk("11223\n");
	// }
	/* Ar803x phy SmartEEE feature cause link status generates glitch,
		* which cause ethernet link down/up issue, so disable SmartEEE
		*/
	phy_write(phydev, 0xd, 0x3);
	phy_write(phydev, 0xe, 0x805d);
	phy_write(phydev, 0xd, 0x4003);

	val = phy_read(phydev, 0xe);
	phy_write(phydev, 0xe, val & ~(1 << 8));

	/*check phy power*/
	val = phy_read(phydev, 0x0);
	if (val & BMCR_PDOWN)
			phy_write(phydev, 0x0, val & ~BMCR_PDOWN);

	// phy_write(phydev, 0x1d, 0x5); /* Address debug register 5 */
	// phy_write(phydev, 0x1e, 0x2d47); /* Value copied from u-boot */
	// phy_write(phydev, 0x1d, 0x0);
	// phy_write(phydev, 0x1e, 0x82ee);
	// phy_write(phydev, 0x1d, 0xb);    /* Address hib ctrl */
	// phy_write(phydev, 0x1e, 0xbc20); /* Value copied from u-boot */

	return 0;
}

设备树如下：

&mac_sw {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	dual_emac = <2>;
};

&davinci_mdio_sw {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	// reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
	// reset-delay-us = <200>;   /* PHY datasheet states 200us min */
	ethphy0: ethernet-phy@1 {
		reg = <1>;
	};
	ethphy1: ethernet-phy@2 {
		reg = <2>;
	};
};

&cpsw_port1 {
	status = "okay";
	phy-mode = "rgmii-id";
	// phy-mode = "rgmii-rxid";
	phy-handle = <&ethphy0>;
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	status = "okay";
	phy-mode = "rgmii-id";
	// phy-mode = "rgmii-rxid";
	phy-handle = <&ethphy1>;
	ti,dual-emac-pvid = <2>;
};

引脚配置:

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE2)			/* mii1_txen.rgmii1_tctl */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2)			/* mii1_rxdv.rgmii1_rctl */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)			/* mii1_txd3.rgmii1_td3 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)			/* mii1_txd2.rgmii1_td2 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)			/* mii1_txd1.rgmii1_td1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)			/* mii1_txd0.rgmii1_td0 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2)			/* mii1_txclk.rgmii1_tclk */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2)			/* mii1_rxclk.rgmii1_rclk */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2)				/* mii1_rxd3.rgmii1_rd3 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2)				/* mii1_rxd2.rgmii1_rd2 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2)				/* mii1_rxd1.rgmii1_rd1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2)				/* mii1_rxd0.rgmii1_rd0 */

			/* Slave 2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a0.rgmii2_tctl */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a1.rgmii2_rctl */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a2.rgmii2_td3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a3.rgmii2_td2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a4.rgmii2_td1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a5.rgmii2_td0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE2)	       			/* gpmc_a6.rgmii2_tclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a7.rgmii2_rclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a8.rgmii2_rd3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a9.rgmii2_rd2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a10.rgmii2_rd1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	       		/* gpmc_a11.rgmii2_rd0 */
		>;				
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
		
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;

	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
			/* Ethernet */
			/*AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT_PULLUP, MUX_MODE7)	 Ethernet_nRST - MCASP0_FSR.gpio3_19 */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

posted @ 2026-06-25 13:48 杨旭0324 阅读(11) 评论(0) 收藏举报

刷新页面返回顶部

Doroの歐潤吉

本博客就当个人笔记随便发发，记录一下，并不严谨。感谢互联网上大佬的开源和分享。

AM335x的双网口+AR8035

环境

内核版本

硬件描述

问题描述

分析过程

解决

公告

Doroの歐潤吉

本博客就当个人笔记随便发发，记录一下，并不严谨。 感谢互联网上大佬的开源和分享。

AM335x的双网口+AR8035

环境

内核版本

硬件描述

问题描述

分析过程

解决

公告

本博客就当个人笔记随便发发，记录一下，并不严谨。感谢互联网上大佬的开源和分享。