xilinx tpg 彩条

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 功能

1.  单axi-stream 接口输入，axis输出。（ 10bit rbg输出）

 

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2. 使用xilinx hls 编写。

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3. 配置寄存器有

 

	#pragma HLS INTERFACE s_axilite  port=height //宽
	#pragma HLS INTERFACE s_axilite  port=width  //高

效果

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   支持

                支持xilinx 所有系列fpga

                               

仿真

图像输出开始

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 一行图像

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 图像结束

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// 0x00 : Control signals
//        bit 0  - ap_start (Read/Write/COH)
//        bit 1  - ap_done (Read/COR)
//        bit 2  - ap_idle (Read)
//        bit 3  - ap_ready (Read)
//        bit 7  - auto_restart (Read/Write)
//        others - reserved
// 0x04 : Global Interrupt Enable Register
//        bit 0  - Global Interrupt Enable (Read/Write)
//        others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
//        bit 0  - enable ap_done interrupt (Read/Write)
//        bit 1  - enable ap_ready interrupt (Read/Write)
//        others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
//        bit 0  - ap_done (COR/TOW)
//        bit 1  - ap_ready (COR/TOW)
//        others - reserved
// 0x10 : Data signal of width
//        bit 31~0 - width[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of height
//        bit 31~0 - height[31:0] (Read/Write)
// 0x1c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

#define XTPG_CONTROL_ADDR_AP_CTRL     0x00
#define XTPG_CONTROL_ADDR_GIE         0x04
#define XTPG_CONTROL_ADDR_IER         0x08
#define XTPG_CONTROL_ADDR_ISR         0x0c
#define XTPG_CONTROL_ADDR_WIDTH_DATA  0x10
#define XTPG_CONTROL_BITS_WIDTH_DATA  32
#define XTPG_CONTROL_ADDR_HEIGHT_DATA 0x18
#define XTPG_CONTROL_BITS_HEIGHT_DATA 32

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