2019年7月20日

Verilog写入变量值到文件语句

摘要: integer signed fid_out1,fid_out2; initial begin fid_out1 = $fopen("dataout_i.txt","w"); fid_out2 = $fopen("dataout_q.txt","w"); end always @(posedge c 阅读全文

posted @ 2019-07-20 12:10 阿长长 阅读(518) 评论(0) 推荐(0)

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