Verilog写入变量值到文件语句
integer signed fid_out1,fid_out2;
initial
begin
fid_out1 = $fopen("dataout_i.txt","w");
fid_out2 = $fopen("dataout_q.txt","w");
end
always @(posedge clk)
begin
if(out_flag)
begin
$fdisplay(fid_out1,"%d",data_I);
$fdisplay(fid_out2,"%d",data_Q);
end
end
