电压采集

 

 

module	Voltage_Meas
(
input				clk,
input				rst_n,

output				adc_cs,
output				adc_clk,
input				adc_dat,

output	[8:0]		seg_1,
output	[8:0]		seg_2

);

wire clk_24mhz;
PLL pll
(
.CLKI				(clk			), //12MHz系统时钟输入
.CLKOP				(clk_24mhz		)  //24MHz时钟输出
);

wire	adc_done;
wire	[7:0]	adc_data;

ADC081S101_dirver adc
(
.clk				(clk_24mhz		),	//系统时钟
.rst_n				(rst_n			),	//系统复位，低有效
.adc_cs				(adc_cs			),	//SPI总线CS
.adc_clk			(adc_clk		),	//SPI总线SCK
.adc_dat			(adc_dat		),	//SPI总线SDA
.adc_done			(adc_done		),	//ADC采样完成标志
.adc_data			(adc_data		)	//ADC采样数据
);
//将ADC采样数据按规则转换为电压数据（乘以0.0129），这里我们直接乘以129，得到的数据经过BCD转码后小数点左移4位即可
wire	[15:0]	bin_code = adc_data *16'd129;
wire	[19:0]	bcd_code;

bin_to_bcd	bin_to_bcd
(
	.rst_n		(rst_n)	,
	.bin_code	(bin_code)	,//需要进行BCD转码的二进制数据

	.bcd_code 	(bcd_code)//转码后的BCD码型数据输出
);

//个位数码管模块例化	
Segment_led seg1
(
.seg_dot			(1'b1			),	//seg_dot input
.seg_data			(bcd_code[19:16]),	//seg_data input
.segment_led		(seg_1			)	//MSB~LSB = SEG,DP,G,F,E,D,C,B,A
);

//分位数码管模块例化
Segment_led seg2
(
.seg_dot			(1'b0			),	//seg_dot input
.seg_data			(bcd_code[15:12]),	//seg_data input
.segment_led		(seg_2			)	//MSB~LSB = SEG,DP,G,F,E,D,C,B,A
);	
	

endmodule

　　

module	Segment_led
(
	input			seg_dot,		//seg_dot input
	input	[3:0]	seg_data,		//seg_dot input
	output	[8:0]	segment_led  	//MSB~LSB = SEG,DP,G,F,E,D,C,B,A
);

reg	[6:0]	segment;

always@(seg_data)
	case (seg_data)
		4'd0: segment = 7'h3f;
		4'd1: segment = 7'h06;
		4'd2: segment = 7'h5b;
		4'd3: segment = 7'h4f;
		4'd4: segment = 7'h66;
		4'd5: segment = 7'h6d;
		4'd6: segment = 7'h7d;
		4'd7: segment = 7'h07;
		4'd8: segment = 7'h7f;
		4'd9: segment = 7'h6f;
		default: segment = 7'h00;
	endcase

assign	segment_led = {1'b0,seg_dot,segment};

endmodule

　　

module	ADC081S101_dirver
(
input				clk,		//系统时钟
input				rst_n,		//系统复位，低有效

output	reg			adc_cs,		//SPI总线CS
output	reg			adc_clk,	//SPI总线SCK
input				adc_dat,	//SPI总线SDA

output	reg			adc_done,	//ADC采样完成标志
output	reg	[7:0]	adc_data	//ADC采样数据
);

localparam	HIGH = 1'b1;
localparam	LOW	= 1'b0;

reg	[7:0]	cnt;   //采样计数器

always@(posedge	clk	or negedge rst_n)
	if(!rst_n)
		cnt <= 8'd0;
	else if(cnt >= 8'd34)
		cnt <= 8'd0;
	else
		cnt <= cnt + 8'd1;
		
reg	[7:0]	data;//数据缓存

always@(posedge clk or negedge	rst_n)
	if(!rst_n)
		begin
			adc_cs <= HIGH;
			adc_clk <= HIGH;
		end
	else	case(cnt)
				8'd0 : begin adc_cs <= HIGH; adc_clk <= HIGH; end
				8'd1 : begin adc_cs <= LOW ; adc_clk <= HIGH; end
				8'd2,8'd4,8'd6,8'd8,8'd10,8'd12,8'd14,8'd16,
				8'd18,8'd20,8'd22,8'd24,8'd26,8'd28,8'd30,8'd32:
					    begin adc_cs <= LOW; adc_clk <= LOW; end
				8'd3  : begin adc_cs <= LOW; adc_clk <= HIGH; end //0
				8'd5  : begin adc_cs <= LOW; adc_clk <= HIGH; end //1
				8'd7  : begin adc_cs <= LOW; adc_clk <= HIGH; end //2	
				8'd9  : begin adc_cs <= LOW; adc_clk <= HIGH; data[7] <= adc_dat; end //3
				8'd11 : begin adc_cs <= LOW; adc_clk <= HIGH; data[6] <= adc_dat; end //4
				8'd13 : begin adc_cs <= LOW; adc_clk <= HIGH; data[5] <= adc_dat; end //5
				8'd15 : begin adc_cs <= LOW; adc_clk <= HIGH; data[4] <= adc_dat; end //6
				8'd17 : begin adc_cs <= LOW; adc_clk <= HIGH; data[3] <= adc_dat; end //7
				8'd19 : begin adc_cs <= LOW; adc_clk <= HIGH; data[2] <= adc_dat; end //8
				8'd21 : begin adc_cs <= LOW; adc_clk <= HIGH; data[1] <= adc_dat; end //9
				8'd23 : begin adc_cs <= LOW; adc_clk <= HIGH; data[0] <= adc_dat; end //10
				8'd25 : begin adc_cs <= LOW; adc_clk <= HIGH; adc_data <= data; end //11
				8'd27 : begin adc_cs <= LOW; adc_clk <= HIGH; adc_done <= HIGH; end //12
				8'd29 : begin adc_cs <= LOW; adc_clk <= HIGH; adc_done <= LOW ; end //13	
				8'd31 : begin adc_cs <= LOW; adc_clk <= HIGH; end //14
				8'd33 : begin adc_cs <= LOW; adc_clk <= HIGH; end //15
				8'd34 : begin adc_cs <= HIGH; adc_clk <= HIGH; end 
				default: begin adc_cs <= HIGH;  adc_clk <= HIGH;  end
		endcase
		

endmodule

　　

module	bin_to_bcd
(
input				rst_n,
input	[15:0]		bin_code,//需要进行BCD转码的二进制数据

output	reg[19:0]	bcd_code //转码后的BCD码型数据输出
);

reg	[35:0]	shift_reg;

always@(bin_code or rst_n)
	begin
		shift_reg ={20'h0,bin_code};
		if(!rst_n)
			bcd_code = 0;
		else begin
				repeat(16)
					begin
						if(shift_reg[19:16] >= 5) shift_reg[19:16] = shift_reg[19:16] +2'b11;
						if(shift_reg[23:20] >= 5) shift_reg[23:20] = shift_reg[23:20] +2'b11;
						if(shift_reg[27:24] >= 5) shift_reg[27:24] = shift_reg[27:24] +2'b11;		
						if(shift_reg[31:28] >= 5) shift_reg[31:28] = shift_reg[31:28] +2'b11;
						if(shift_reg[35:32] >= 5) shift_reg[35:32] = shift_reg[35:32] +2'b11;	
						shift_reg = shift_reg << 1;
					end
			    bcd_code = shift_reg[35:16];
			end
	end
	
endmodule