小小计算器之消零显示模块数码管消零

 

module display3(clk, rst_n,adata, bdata, sel, seg, clk_slow);
   input clk;
    input rst_n;

    input [24:0] adata,bdata;

    output reg [2:0] sel;
    output reg [7:0] seg;

    wire  [24:0] data;
    reg [3:0] segdata;
    reg [15:0] cnt;
    reg [23:0] data_1;
    output reg clk_slow;
    

    assign data =(bdata == 0) ? adata : bdata;
    

    always @ (posedge clk or negedge rst_n)   
    begin 
        if(!rst_n)
        begin
            cnt <= 0;
            clk_slow <= 1;
        end
        else
        begin
            cnt <= cnt + 1; 
            clk_slow <= cnt[12]; 
        end
    end    


always @(posedge clk_slow or negedge rst_n )

begin
    if(!rst_n)
        data_1<=24'hffffff;
    else
 casex(data)
//  25'h100000x: data_1<={20'hffffa ,data[3:0]}  ;           
//  25'h10000xx: data_1<={16'hfffa  ,data[7:0]}  ;           
  25'h1000xxx: data_1<={12'hffa   ,data[11:0]} ;            
  25'h100xxxx: data_1<={8'hfa    ,data[15:0]}  ;            
  25'h10xxxxx: data_1<={4'ha     ,data[19:0]}  ;            
//  25'h000000x: data_1<={20'hfffff ,data[3:0]}  ;           
//  25'h00000xx: data_1<={16'hffff  ,data[7:0]}  ;           
  25'h0000xxx: data_1<={12'hfff   ,data[11:0]} ;            
  25'h000xxxx: data_1<={8'hff    ,data[15:0]}  ;            
  25'h00xxxxx: data_1<={4'hf     ,data[19:0]}  ;    
  default: data_1 =data ;        
 endcase                                            
end 

always @ (posedge clk_slow or negedge rst_n)   
    begin
        if(!rst_n)
        begin
            sel <= 0;
        end
        else
        begin
            sel <= sel + 1;
            if (sel >= 5)
                sel <= 0;
        end
    end

    always @ (sel or rst_n) 
    begin
        if(!rst_n)
        begin
            segdata <= 0;
        end
        else
        begin
           case(sel)
                5:  segdata <= data_1[3:0];     //低四位
                4:  segdata <= data_1[7:4];     
                3:  segdata <= data_1[11:8];    
                2:  segdata <= data_1[15:12];   
                1:  segdata <= data_1[19:16];   
                0:  segdata <= data_1[23:20];  
            default:  segdata <= 0;
           endcase
        end
    end

    always @ (sel or rst_n or segdata) 
    begin
        if(!rst_n)
        begin
            seg <= 8'hff;
        end
        else
        begin
        if(sel != 3)
          case(segdata)
                4'h0: seg <= 8'b11000000;
                4'h1: seg <= 8'b11111001;
                4'h2: seg <= 8'b10100100;
                4'h3: seg <= 8'b10110000;
                4'h4: seg <= 8'b10011001;
                4'h5: seg <= 8'b10010010;
                4'h6: seg <= 8'b10000010;
                4'h7: seg <= 8'b11111000;
                4'h8: seg <= 8'b10000000;
                4'h9: seg <= 8'b10010000;
              4'ha: seg <= 8'b10111111;
            default: seg <= 8'b11111111;
        endcase
      else
        case(segdata)
                4'h0: seg <= 8'b01000000;
                4'h1: seg <= 8'b01111001;
                4'h2: seg <= 8'b00100100;
                4'h3: seg <= 8'b00110000;
                4'h4: seg <= 8'b00011001;
                4'h5: seg <= 8'b00010010;
                4'h6: seg <= 8'b00000010;
                4'h7: seg <= 8'b01111000;
                4'h8: seg <= 8'b00000000;
                4'h9: seg <= 8'b00010000;
               4'ha: seg <= 8'b00111111;
            default: seg <= 8'b01111111;
      endcase
    end
end
endmodule

计算器数码管显示模块做运算的时候，若果不作处理，除了输入的数据前面还会显示零，折让我们追求完美的人看来是很不爽的，那么如何做到消零呢，这就要介绍一种比较简单的用法的就是verilog语法里的casex语句，详细的用法以及casez请参考夏宇闻老师的书籍，

casex到底怎么用，其实他和case差不多，只是多了个x，我们都知道，数电里面有高电平1，低电平0，不定态X，高阻态Z。所谓不定态就是不知道它 是0还是1。所以放在我们这段代码里意思就是不管x所代表的是0还是1，我都满足casex的条件。如果判断出一个数的前5位都是0，那么我们就给他的前 五位赋值成熄灭码，也就是在数码管译码的时候译成全1的值（数码管是共阳）。这里还有一个地方得注意，假如一个数前5位都是0，那是不是以为着，上面5种 情况他都满足，那他到底执行哪一种呢？其实case、casex和if else一样是有优先级的，写在最上面的优先级最高。所以判断是否有5个0的，一定要赋予它最高的优先级。

按照上面显示就可以实现消零的目的。