【笔记】Verilog怎么把for也整合过来

参考<<Verilog那些事儿-整合篇>>

 

一：模仿一个for循环

for(Act1 = 0; Act1 < 10; Act1 ++)

case (i)
    0 : 
    begin
        if (x == C1)
            begin
                x <= x + 1'b1;  
                Act1 <= Act1 + 1'b1; //x == 9时,这里Act1就为10了
            end
            
        if (C1 == 10 - 1)
            begin
                x <= 8'd0;
                C1 <= 8'd0;
                i <= i + 1'b1;
            end
        
        else
            C1 <= C1 + 1'b1;
    end
    
    1 : 
    begin
        C1 <= 8'd10;
        x <= 8'd20;
        Act <= 8'd30;
        i <= 4'd1;
    end
    

仿真图：

 

 

二：模仿2个for

for (int x = 0; x < 10; x ++)

{

　　Act1 ++;

　　for (int y = 0; y < 10; y ++)

　　　　Act2 ++;

}

case (i)    
    
    0 :
    begin
        if (x == C1)
        begin
            x <= x + 8'd10;  //hey，这里是加10哦
            Act1 <= Act1 + 1'b1;
        end
        
        if (y == C1)
        begin
            y <= y + 1'b1;
            Act2 <= Act2 + 1'b1;
        end
        
        if (C1 == 100 - 1)
        begin
            x <= 8'd0;
            y <= 8'd0;
            C1 <= 8'd0;
            i <= i + 1;
        end
    end

仿真图