VHDL模板
摘自alter在线视频的ppt
常量
-命名相关值
-常量声明
CONSTANT <name> : <DATA_TYPE> :=
<value>;
CONSTANT bus_width : INTEGER := 16;
-执行代码不能改变它
-提高代码的可读性
-提高代码的灵活性
信号
-表示物理互联（线）的信号，实现进程之间的通
信（函数）
-信号可以在封装，实体和体系结构中进行声明
为信号赋值
SIGNAL temp : STD_LOGIC_VECTOR (7 DOWNTO 0);
-所有比特：
temp <= "10101010";
temp <= x"AA" --十六进制
-单比特：
temp (7) <= '1';
-比特分割
temp (7 DOWNTO 0) <= "1010";
-单比特： 单引号 （'）
-多比特： 双引号 （"）
用作互联的信号
ENTITY simp IS
PORT (
i1, i2 : IN BIT;
0 : OUT BIT
);
END ENTITY simp;
ARCHITECTURE logic OF simp IS
SIGNAL int : BIT;
BEGIN
int <= i1 | i2;
o <= NOT int;
END ARCHITECTURE logic;
算子加载
-VHDL只为内置数据类型定义算术和布尔函数（在
标准封装中定义）
- +,-,<,>,<=,>=等算术算子只定义为INTEGER
类型
-AND,OR,NOT等布尔算子只定义为BIT类型
-算术&布尔函数怎样和其他数据类型一起使用？
-算子加载 -定义算术&布尔函数和其他数据类
型
-通过定义名称和算子本身一样的函数来加载算子
-由于算子和函数名称相同，因此，函数名称
必须在双引号内，以便和实际VHDL算子区分
-函数一般在封装中进行声明，这样，在任何
设计中都可以实现全局可视。
算子加载函数/封装
-可以在LIBRARY IEEE中找到定义这些算子加载函
数的封装
-std_logic_arith (算术函数)
-std_logic_signed (符号算术函数)
-std_logic_unsigned (无符号算术函数)
-numeric_std (符号和无符号算术)
使用算子加载
--在设计文件的开始包括这些声明
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY overload IS
PORT (
a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
sum : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
);
END ENTITY overload;
ARCHITECTURE example OF overload IS
BEGIN
sum <= a + b;
--可以利用它对非内置数据类型进行算术运算
END ARCHITECTURE example;
条件信号赋值
-格式
<signal_name> <= <signal/value> when
<condition1> else
<signal_name> <= <signal/value> when
<condition2> else
.
.
.
<signal_name> <= <signal/value> when
<condition3> else
-例子
q < a WHEN sela = '1' ELSE
b WHEN selb = '1' ELSE
c;
选择信号赋值
-格式：
with <expression> select
<signal_name> <= <signal/value> when
<condition1>
<signal_name> <= <signal/value> when
<condition2>
.
.
.
<signal_name> <= <signal/value> when
<condition3>
显示进程声明
-一直执行进程声明，除非被WAIT声明或者敏感事
件列表打断
-敏感事件列表在进程的最后隐含了一个WAIT
声明
-进程可以有多个WAIT声明
-进程不能同时有敏感事件列表和WAIT声明
-内部含顺序声明
-同时声明
-一个体系结构可以有多个进程声明
-所有显示进程并行执行
--Explicit process statement
label: PROCESS (sensivity_list)
Constant declarations
Variable declarations
BEGIN
--Sequential statement #1;
--......
--Sequential statement #0;
END PROCESS;
进程声明实例
procl: PROCESS (a, b)
BEGIN
---Sequential statements
END PROCESS;
proc2: PROCESS
BEGIN
---Sequential statements
WAIT ON (a, b);
END PROCESS;
IF_THEN声明
-格式：
IF <condition1> THEN
{sequence of statement (s)}
ELSIF <condition2> THEN
{sequence of statement (s)}
.
.
ELSE
{sequence of statement (s)}
END IF;
-例子：
PROCESS (sela, selb, a, b, c)
BEGIN
IF sela = '1' THEN
q <= a;
ELSIF selb = '1' THEN
q <= b;
ELSE
q <= c;
END IF;
END PROCESS;
CASE声明
-格式：
CASE {expression} IS
WHEN <condition1> =>
{sequence of statements}
WHEN <conditon2> =>
{sequence of statements}
.
.
WHEN OTHERS => --(optional)
{sequence of statements}
END CASE;
-例子：
PROCESS (sel, a, b, c, d)
BEGIN
CASE sel IS
WHEN "00" =>
q <= a;
WHEN "01" =>
q <= b;
WHEN "10" =>
q <= c;
WHEN OTHERS =>
q <= d;
END CASE;
END PROCESS;
顺序循环
-LOOP声明
-无限循环，除非出现EXIT声明
-WHILE循环
-条件测试循环结束
-FOR循环
-反复循环
[loop_label] LOOP
--sequential statement
NEXT loop_label WHEN ...;
EXIT loop_label WHEN ...;
END LOOP;
WHILE <condition> LOOP
--sequential statements
END LOOP;
FOR <identifier> IN <range> LOOP
--sequential statements
END LOOP;
WAIT声明
-WATI ON <signal>
-暂停，直到信号事件发生
WAIT ON a, b;
-WAIT UNTIL <boolean_expression>
-暂停，直到布尔表达式为真
WAIT UNTIL (int < 100);
-WAIT FOR <time_expression>
-暂停，直到经过了表达式指定的时间
WAIT FOR 20ns
-可以组合使用
WAIT UNTIL (a = '1') FOR 5us;s
*wait声明在综合中的使用有限
等价函数
--1
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL
ENTITY simp IS
PORT (
a, b : IN std_logic;
y : OUT std_logic
);
END ENTITY simp;
ARCHITECTURE logic OF simp IS
SIGNAL c : std_logic;
BEGIN
c <= a AND b;
y <= c;
END ARCHITECTURE logic;
--2
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY simp_prc IS
PORT (
a, b : IN std_logic;
y : OUT std_logic
);
END ENTITY simp_prc;
ARCHITECTURE logic OF simp_prc IS
SIGNAL c : std_logic;
BEGIN
Process1: PROCESS (a, b)
BEGIN
c <= a AND b;
END PROCESS Process1;
Process2: PROCESS (c)
BEGIN
y <= c;
END PROCESS Process2;
END ARCHITECTURE logic;
不等价函数
--1
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY simp IS
PORT (
a, b : IN std_logic;
y : OUT std_logic
);
END ENTITY simp;
ARCHITECTURE logic OF simp IS
SIGNAL c : std_logic;
BEGIN
c <= a AND b;
y <= c;
END ARCHITECTURE logic;
--2
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY simp IS
PORT (
a, b : IN std_logic;
y : OUT std_logic
);
END ENTITY simp;
ARCHITECTURE logic OF simp IS
SIGNAL c : std_logic;
BEGIN
PROCESS (a, b)
BEGIN
c <= a AND b;
y <= c;
END PROCESS;
END ARCHITECTURE logic;
变量声明
-在进程内部声明变量
-变量赋值表示为:-
-变量声明
-VARIABLE <name> : <DATA_TYPE> :=
<VALUE>
-VARIABLE temp : std_logic_vector (7
DOWNTO 0);
-立即更新变量赋值
-不会出现延迟
数组
-建立2维数据类型以储存数值
-必须建立该类型的常量，信号或者变量
-用于建立存储器和储存仿真矢量
-数组类型声明
TYPE <array_type_name> IS ARRAY
(<integer_range>) OF <data_type>;
数组实例
ARCHITECTURE logic OF my_memory IS
TYPE mem IS ARRAY (0 TO 63) OF
std_logic_vector (7 DOWNTO 0);
--Creat new array data type named mem
which has 64
--address locations each 8 bits wide
SIGNAL mem_64x8_a, mem_64x8_b : mem;
--Creat 2-64x8-bit arrays to use in
design
BEGIN
mem_64x8_a(12) <= x "A4";
mem_64x8_b(50) <= "11110000";
END ARCHITECTURE logic;
枚举数据类型
-使用户能够建立数据类型 名称和数值
-必须建立该类型的常量，信号或者变量
-用于
-使代码更具有可读性
-有限状态机
-枚举类型声明
TYPE <your_data_type> IS
(data type items or values separated by
commas);
eg
TYPE enum IS (idle, fill, heat_w, wash,
drain);
SIGNAL dshwshr_st : enum;
.
.
drain_led <= '1' WHEN dshwsher_st = drain
ELSE '0';
DFF使用rising_edge
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_b IS
PORT (
clk, d : IN std_logic;
q : OUT std_logic
);
END ENTITY dff_b;
ARCHITECTURE rtl OF dff_b IS
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge (clk) THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
rising_edge(和falling_edge)
-在std_logic_1164封装中定义IEEE函数
-指定信号值必须是0到1（或者1到0）
-不允许X,Z到1转换
clk'event and clk = '1'(或者'0')
-不将时钟限制在0到1（或者1到0）的转换
带有异步清除的DFF
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_aclr IS
PORT (
d, clk, clr : IN std_logic;
q : OUT std_logic
);
END ENTITY dff_aclr
ARCHITECTURE rtl OF dff_aclr IS
BEGIN
PROCESS (clk, clr)
BEGIN
IF clr = '0' THEN
q <= '0';
ELSIF rising_edge (clk) THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
带有同步清除的DFF
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_sclr IS
PORT (
d, clk, clr : IN std_logic;
q : OUT std_logic
);
END ENTITY dff_sclr;
ARCHITECTURE rtl OF dff_sclr IS
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge (clk) THEN
IF clr = '0' THEN
q <= '0';
ELSE
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
带有异步清除和时钟使能的DFF
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_aclr_ena IS
PORT (
d, clk, clr, ena : IN std_logic;
q : OUT std_logic
);
ARCHITECTURE rtl OF dff_aclr_ena IS
BEGIN
PROCESS (clk, clr)
BEGIN
IF clr = '0' THEN
q <= '0';
ELSIF rising_edge (clk) THEN
IF ena = '1' THEN
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
计数器
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY counter IS
PORT (
clk, rst : in std_logic;
q : out std_logic_vector (15 DOWNTO 0)
);
END ENTITY counter;
ARCHITECTURE logic OF counter IS
SIGNAL tmp_q : std_logic_vector (15 DOWNTO
0);
BEGIN
PROCESS (clk, rst)
BEGIN
IF rst = '0' THEN
tmp_q <= (OTHERS => '0');
ELSIF rising_edge (clk) THEN
tmp_q <= tmp_q + 1;
END IF;
END PROCESS;
q <= tmp_q;
END ARCHITECTURE logic;
组件声明和例化
-组件声明---用于声明底层设计端口的端口类型和
数据类型
COMPONENT <lower-level_design_name>
PORT (
<port_name> : <port_type> <data_type>;
.
.
<port_name> : <port_type> <data_type>;
);
END COMPONENT;
-组件例化----同时声明，用于吧底层设计的端口
映射到当前层设计。
<instance_name> : <lower-level_design_name>
PORT MAP (<lower-level_port_name> =>
<current_level_port_name>,
...,
<lower-level_port_name> =>
<current_level_port_name>);
组件声明和例化
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tolleanb IS
PORT (
tclk, tcross, tnickel, tdime, tquarter :
IN Std_logic;
tgreen, tred : OUT Std_logic
);
END ENTITY tolleab;
ARCHITECTURE tolleab_arch OF tolleab IS
COMPONENT tollv
PORT (
clk, cross, nickel, dime, quater : IN
std_logic;
green, red : OUT std_logic
);
END COMPONENT
BEGIN
U1 : tollv PORT MAP (clk => tclk, cross =>
tcross, nickel => tnickel, dime => tdime,
quarter => tquarter, green =>tgreen, red =>
tred)
END ARCHITECTURE tolleab_arch;
--Dime（底层端口） => tdime(当前层端口)
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