ARMv7 指令集中DMB DSB ISB指令的区别

DMB

Data Memory Barrier 数据内存屏障

Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in
program order before the DMB instruction are observed before any explicit memory accesses that appear
in program order after the DMB instruction. It does not affect the ordering of any other instructions
executing on the processor.[1]

尝试翻译：

DMB 起到内存屏障的作用。它确保了所有程序顺序出现在DMB指令前的显式内存访问可以被DMB指令后的显式内存访问观察到。它不会影响处理器上其他指令的执行顺序。

我的理解：DMB指令仅用于确保DMB前的显式内存访问完成后才能执行后面的显式内存访问
即：显式内存访问完成->DMB->显式内存访问开始

DSB

Data Synchronization Barrier 数据同步屏障

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order
after this instruction executes until this instruction completes. This instruction completes when:
• All explicit memory accesses before this instruction complete.
• All Cache, Branch predictor and TLB maintenance operations before this instruction complete.[1]

尝试翻译：

数据同步屏障是一种特殊的内存屏障。
直至此指令执行完成，在不会执行任何其他指令，此指令在以下情况下执行完毕：
• 在此指令之前的所有显式内存访问均已完成。
• 在此指令之前的所有缓存、分支预测器和TLB维护操作均已完成。

我的理解:在DMB的基础上，进一步增加了对缓存、分支预测器和TLB维护操作的顺序控制，确保其前面的所有内存访问操作完成。
即：所有内存访问完成->DSB->任意指令开始

ISB

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following
the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the
effects of context altering operations, such as changing the ASID, or completed TLB maintenance
operations, or branch predictor maintenance operations, in addition to all changes to the CP15 registers,
executed before the ISB instruction are visible to the instructions fetched after the ISB.
In addition, the ISB instruction ensures that any branches that appear in program order after it are always
written into the branch prediction logic with the context that is visible after the ISB instruction. This is
required to ensure correct execution of the instruction stream.[1]

尝试翻译：

指令同步屏障刷新处理器的流水线，以便ISB指令完成后，使ISB后的所有指令从cache或内存重新获取(fetch)。
它确保在ISB指令之前执行的上下文更改操作（如更改ASID）、已完成的TLB维护操作、分支预测器维护操作，以及所有对CP15寄存器的更改，对ISB之后重新获取的指令可见。
此外，ISB指令确保在此之后按程序顺序出现的任何分支，总是写入分支预测逻辑中（使用ISB指令之后可见的上下文）。
这是确保指令流正确执行所必需的。

我的理解：确保ISB指令前后的所有指令在执行时不得跨越指令同步屏障所划分的前后顺序
即：任意指令完成->ISB刷新流水线->任意指令取值

参考文献

[1] Instruction Set Assembly Guide for Armv7 and earlier Arm architectures Reference Guide